xref: /rk3399_rockchip-uboot/arch/arm/dts/fsl-ls2081a-rdb.dts (revision 380e86f361e4e2aef83295972863654fde157560)
1*3049a583SPriyanka Jain/*
2*3049a583SPriyanka Jain * NXP LS2081A RDB board device tree source for QSPI-boot
3*3049a583SPriyanka Jain *
4*3049a583SPriyanka Jain * Author: Priyanka Jain <priyanka.jain@nxp.com>
5*3049a583SPriyanka Jain *
6*3049a583SPriyanka Jain * Copyright 2017 NXP
7*3049a583SPriyanka Jain *
8*3049a583SPriyanka Jain * SPDX-License-Identifier:	GPL-2.0+
9*3049a583SPriyanka Jain */
10*3049a583SPriyanka Jain
11*3049a583SPriyanka Jain/dts-v1/;
12*3049a583SPriyanka Jain
13*3049a583SPriyanka Jain#include "fsl-ls2080a.dtsi"
14*3049a583SPriyanka Jain
15*3049a583SPriyanka Jain/ {
16*3049a583SPriyanka Jain	model = "Freescale Layerscape 2081a RDB Board";
17*3049a583SPriyanka Jain	compatible = "fsl,ls2081a-rdb", "fsl,ls2080a";
18*3049a583SPriyanka Jain
19*3049a583SPriyanka Jain	aliases {
20*3049a583SPriyanka Jain		spi0 = &qspi;
21*3049a583SPriyanka Jain		spi1 = &dspi;
22*3049a583SPriyanka Jain	};
23*3049a583SPriyanka Jain};
24*3049a583SPriyanka Jain
25*3049a583SPriyanka Jain&dspi {
26*3049a583SPriyanka Jain	bus-num = <0>;
27*3049a583SPriyanka Jain	status = "okay";
28*3049a583SPriyanka Jain
29*3049a583SPriyanka Jain	dflash0: n25q512a {
30*3049a583SPriyanka Jain		#address-cells = <1>;
31*3049a583SPriyanka Jain		#size-cells = <1>;
32*3049a583SPriyanka Jain		compatible = "spi-flash";
33*3049a583SPriyanka Jain		spi-max-frequency = <3000000>;
34*3049a583SPriyanka Jain		spi-cpol;
35*3049a583SPriyanka Jain		spi-cpha;
36*3049a583SPriyanka Jain		reg = <0>;
37*3049a583SPriyanka Jain	};
38*3049a583SPriyanka Jain};
39*3049a583SPriyanka Jain
40*3049a583SPriyanka Jain&qspi {
41*3049a583SPriyanka Jain	bus-num = <0>;
42*3049a583SPriyanka Jain	status = "okay";
43*3049a583SPriyanka Jain
44*3049a583SPriyanka Jain	qflash0: n25q512a@0 {
45*3049a583SPriyanka Jain		#address-cells = <1>;
46*3049a583SPriyanka Jain		#size-cells = <1>;
47*3049a583SPriyanka Jain		compatible = "spi-flash";
48*3049a583SPriyanka Jain		spi-max-frequency = <50000000>;
49*3049a583SPriyanka Jain		reg = <0>;
50*3049a583SPriyanka Jain	};
51*3049a583SPriyanka Jain
52*3049a583SPriyanka Jain	qflash1: n25q512a@1 {
53*3049a583SPriyanka Jain		#address-cells = <1>;
54*3049a583SPriyanka Jain		#size-cells = <1>;
55*3049a583SPriyanka Jain		compatible = "spi-flash";
56*3049a583SPriyanka Jain		spi-max-frequency = <50000000>;
57*3049a583SPriyanka Jain		reg = <1>;
58*3049a583SPriyanka Jain	};
59*3049a583SPriyanka Jain};
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