1/* 2 * Device Tree Include file for Freescale Layerscape-1043A family SoC. 3 * 4 * Copyright (C) 2014-2015, Freescale Semiconductor 5 * 6 * Mingkai Hu <Mingkai.hu@freescale.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13/include/ "skeleton64.dtsi" 14 15/ { 16 compatible = "fsl,ls1043a"; 17 interrupt-parent = <&gic>; 18 cpus { 19 #address-cells = <2>; 20 #size-cells = <0>; 21 22 cpu0: cpu@0 { 23 device_type = "cpu"; 24 compatible = "arm,cortex-a53"; 25 reg = <0x0 0x0>; 26 clocks = <&clockgen 1 0>; 27 }; 28 29 cpu1: cpu@1 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a53"; 32 reg = <0x0 0x1>; 33 clocks = <&clockgen 1 0>; 34 }; 35 36 cpu2: cpu@2 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a53"; 39 reg = <0x0 0x2>; 40 clocks = <&clockgen 1 0>; 41 }; 42 43 cpu3: cpu@3 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a53"; 46 reg = <0x0 0x3>; 47 clocks = <&clockgen 1 0>; 48 }; 49 }; 50 51 sysclk: sysclk { 52 compatible = "fixed-clock"; 53 #clock-cells = <0>; 54 clock-frequency = <100000000>; 55 clock-output-names = "sysclk"; 56 }; 57 58 gic: interrupt-controller@1400000 { 59 compatible = "arm,gic-400"; 60 #interrupt-cells = <3>; 61 interrupt-controller; 62 reg = <0x0 0x1401000 0 0x1000>, /* GICD */ 63 <0x0 0x1402000 0 0x2000>, /* GICC */ 64 <0x0 0x1404000 0 0x2000>, /* GICH */ 65 <0x0 0x1406000 0 0x2000>; /* GICV */ 66 interrupts = <1 9 0xf08>; 67 }; 68 69 soc { 70 compatible = "simple-bus"; 71 #address-cells = <2>; 72 #size-cells = <2>; 73 ranges; 74 75 clockgen: clocking@1ee1000 { 76 compatible = "fsl,ls1043a-clockgen"; 77 reg = <0x0 0x1ee1000 0x0 0x1000>; 78 #clock-cells = <2>; 79 clocks = <&sysclk>; 80 }; 81 82 ifc: ifc@1530000 { 83 compatible = "fsl,ifc", "simple-bus"; 84 reg = <0x0 0x1530000 0x0 0x10000>; 85 interrupts = <0 43 0x4>; 86 }; 87 88 i2c0: i2c@2180000 { 89 compatible = "fsl,vf610-i2c"; 90 #address-cells = <1>; 91 #size-cells = <0>; 92 reg = <0x0 0x2180000 0x0 0x10000>; 93 interrupts = <0 56 0x4>; 94 clock-names = "i2c"; 95 clocks = <&clockgen 4 0>; 96 status = "disabled"; 97 }; 98 99 i2c1: i2c@2190000 { 100 compatible = "fsl,vf610-i2c"; 101 #address-cells = <1>; 102 #size-cells = <0>; 103 reg = <0x0 0x2190000 0x0 0x10000>; 104 interrupts = <0 57 0x4>; 105 clock-names = "i2c"; 106 clocks = <&clockgen 4 0>; 107 status = "disabled"; 108 }; 109 110 i2c2: i2c@21a0000 { 111 compatible = "fsl,vf610-i2c"; 112 #address-cells = <1>; 113 #size-cells = <0>; 114 reg = <0x0 0x21a0000 0x0 0x10000>; 115 interrupts = <0 58 0x4>; 116 clock-names = "i2c"; 117 clocks = <&clockgen 4 0>; 118 status = "disabled"; 119 }; 120 121 i2c3: i2c@21b0000 { 122 compatible = "fsl,vf610-i2c"; 123 #address-cells = <1>; 124 #size-cells = <0>; 125 reg = <0x0 0x21b0000 0x0 0x10000>; 126 interrupts = <0 59 0x4>; 127 clock-names = "i2c"; 128 clocks = <&clockgen 4 0>; 129 status = "disabled"; 130 }; 131 132 duart0: serial@21c0500 { 133 compatible = "fsl,ns16550", "ns16550a"; 134 reg = <0x00 0x21c0500 0x0 0x100>; 135 interrupts = <0 54 0x4>; 136 clocks = <&clockgen 4 0>; 137 }; 138 139 duart1: serial@21c0600 { 140 compatible = "fsl,ns16550", "ns16550a"; 141 reg = <0x00 0x21c0600 0x0 0x100>; 142 interrupts = <0 54 0x4>; 143 clocks = <&clockgen 4 0>; 144 }; 145 146 duart2: serial@21d0500 { 147 compatible = "fsl,ns16550", "ns16550a"; 148 reg = <0x0 0x21d0500 0x0 0x100>; 149 interrupts = <0 55 0x4>; 150 clocks = <&clockgen 4 0>; 151 }; 152 153 duart3: serial@21d0600 { 154 compatible = "fsl,ns16550", "ns16550a"; 155 reg = <0x0 0x21d0600 0x0 0x100>; 156 interrupts = <0 55 0x4>; 157 clocks = <&clockgen 4 0>; 158 }; 159 }; 160}; 161