1*e1cecb4dSGong Qianyu/* 2*e1cecb4dSGong Qianyu * Device Tree Include file for Freescale Layerscape-1043A family SoC. 3*e1cecb4dSGong Qianyu * 4*e1cecb4dSGong Qianyu * Copyright (C) 2015, Freescale Semiconductor 5*e1cecb4dSGong Qianyu * 6*e1cecb4dSGong Qianyu * Mingkai Hu <Mingkai.hu@freescale.com> 7*e1cecb4dSGong Qianyu * 8*e1cecb4dSGong Qianyu * This file is licensed under the terms of the GNU General Public 9*e1cecb4dSGong Qianyu * License version 2. This program is licensed "as is" without any 10*e1cecb4dSGong Qianyu * warranty of any kind, whether express or implied. 11*e1cecb4dSGong Qianyu */ 12*e1cecb4dSGong Qianyu 13*e1cecb4dSGong Qianyu/dts-v1/; 14*e1cecb4dSGong Qianyu/include/ "fsl-ls1043a.dtsi" 15*e1cecb4dSGong Qianyu 16*e1cecb4dSGong Qianyu/ { 17*e1cecb4dSGong Qianyu model = "LS1043A RDB Board"; 18*e1cecb4dSGong Qianyu}; 19*e1cecb4dSGong Qianyu 20*e1cecb4dSGong Qianyu&i2c0 { 21*e1cecb4dSGong Qianyu status = "okay"; 22*e1cecb4dSGong Qianyu ina220@40 { 23*e1cecb4dSGong Qianyu compatible = "ti,ina220"; 24*e1cecb4dSGong Qianyu reg = <0x40>; 25*e1cecb4dSGong Qianyu shunt-resistor = <1000>; 26*e1cecb4dSGong Qianyu }; 27*e1cecb4dSGong Qianyu adt7461a@4c { 28*e1cecb4dSGong Qianyu compatible = "adi,adt7461a"; 29*e1cecb4dSGong Qianyu reg = <0x4c>; 30*e1cecb4dSGong Qianyu }; 31*e1cecb4dSGong Qianyu eeprom@56 { 32*e1cecb4dSGong Qianyu compatible = "at24,24c512"; 33*e1cecb4dSGong Qianyu reg = <0x52>; 34*e1cecb4dSGong Qianyu }; 35*e1cecb4dSGong Qianyu 36*e1cecb4dSGong Qianyu eeprom@57 { 37*e1cecb4dSGong Qianyu compatible = "at24,24c512"; 38*e1cecb4dSGong Qianyu reg = <0x53>; 39*e1cecb4dSGong Qianyu }; 40*e1cecb4dSGong Qianyu 41*e1cecb4dSGong Qianyu rtc@68 { 42*e1cecb4dSGong Qianyu compatible = "pericom,pt7c4338"; 43*e1cecb4dSGong Qianyu reg = <0x68>; 44*e1cecb4dSGong Qianyu }; 45*e1cecb4dSGong Qianyu}; 46*e1cecb4dSGong Qianyu 47*e1cecb4dSGong Qianyu&ifc { 48*e1cecb4dSGong Qianyu status = "okay"; 49*e1cecb4dSGong Qianyu #address-cells = <2>; 50*e1cecb4dSGong Qianyu #size-cells = <1>; 51*e1cecb4dSGong Qianyu /* NOR, NAND Flashes and FPGA on board */ 52*e1cecb4dSGong Qianyu ranges = <0x0 0x0 0x0 0x60000000 0x08000000 53*e1cecb4dSGong Qianyu 0x2 0x0 0x0 0x7e800000 0x00010000 54*e1cecb4dSGong Qianyu 0x3 0x0 0x0 0x7fb00000 0x00000100>; 55*e1cecb4dSGong Qianyu 56*e1cecb4dSGong Qianyu nor@0,0 { 57*e1cecb4dSGong Qianyu compatible = "cfi-flash"; 58*e1cecb4dSGong Qianyu #address-cells = <1>; 59*e1cecb4dSGong Qianyu #size-cells = <1>; 60*e1cecb4dSGong Qianyu reg = <0x0 0x0 0x8000000>; 61*e1cecb4dSGong Qianyu bank-width = <2>; 62*e1cecb4dSGong Qianyu device-width = <1>; 63*e1cecb4dSGong Qianyu }; 64*e1cecb4dSGong Qianyu 65*e1cecb4dSGong Qianyu nand@1,0 { 66*e1cecb4dSGong Qianyu compatible = "fsl,ifc-nand"; 67*e1cecb4dSGong Qianyu #address-cells = <1>; 68*e1cecb4dSGong Qianyu #size-cells = <1>; 69*e1cecb4dSGong Qianyu reg = <0x1 0x0 0x10000>; 70*e1cecb4dSGong Qianyu }; 71*e1cecb4dSGong Qianyu 72*e1cecb4dSGong Qianyu cpld: board-control@2,0 { 73*e1cecb4dSGong Qianyu compatible = "fsl,ls1043ardb-cpld"; 74*e1cecb4dSGong Qianyu reg = <0x2 0x0 0x0000100>; 75*e1cecb4dSGong Qianyu }; 76*e1cecb4dSGong Qianyu}; 77*e1cecb4dSGong Qianyu 78*e1cecb4dSGong Qianyu&duart0 { 79*e1cecb4dSGong Qianyu status = "okay"; 80*e1cecb4dSGong Qianyu}; 81*e1cecb4dSGong Qianyu 82*e1cecb4dSGong Qianyu&duart1 { 83*e1cecb4dSGong Qianyu status = "okay"; 84*e1cecb4dSGong Qianyu}; 85