xref: /rk3399_rockchip-uboot/arch/arm/dts/bk4r1.dts (revision f5fd45ff64e28a73499548358e3d1ceda0de7daf)
1*27192d16SAlbert ARIBAUD \(3ADEV\)/*
2*27192d16SAlbert ARIBAUD \(3ADEV\) * Copyright 2016 Toradex AG
3*27192d16SAlbert ARIBAUD \(3ADEV\) *
4*27192d16SAlbert ARIBAUD \(3ADEV\) * SPDX-License-Identifier:     GPL-2.0+ or X11
5*27192d16SAlbert ARIBAUD \(3ADEV\) */
6*27192d16SAlbert ARIBAUD \(3ADEV\)
7*27192d16SAlbert ARIBAUD \(3ADEV\)/dts-v1/;
8*27192d16SAlbert ARIBAUD \(3ADEV\)#include "vf.dtsi"
9*27192d16SAlbert ARIBAUD \(3ADEV\)
10*27192d16SAlbert ARIBAUD \(3ADEV\)/ {
11*27192d16SAlbert ARIBAUD \(3ADEV\)	model = "Phytec phyCORE-Vybrid";
12*27192d16SAlbert ARIBAUD \(3ADEV\)	compatible = "phytec,pcm052", "fsl,vf610";
13*27192d16SAlbert ARIBAUD \(3ADEV\)
14*27192d16SAlbert ARIBAUD \(3ADEV\)	chosen {
15*27192d16SAlbert ARIBAUD \(3ADEV\)		stdout-path = &uart1;
16*27192d16SAlbert ARIBAUD \(3ADEV\)	};
17*27192d16SAlbert ARIBAUD \(3ADEV\)
18*27192d16SAlbert ARIBAUD \(3ADEV\)	aliases {
19*27192d16SAlbert ARIBAUD \(3ADEV\)		spi0 = &qspi0;
20*27192d16SAlbert ARIBAUD \(3ADEV\)	};
21*27192d16SAlbert ARIBAUD \(3ADEV\)
22*27192d16SAlbert ARIBAUD \(3ADEV\)};
23*27192d16SAlbert ARIBAUD \(3ADEV\)
24*27192d16SAlbert ARIBAUD \(3ADEV\)&uart1 {
25*27192d16SAlbert ARIBAUD \(3ADEV\)	status = "okay";
26*27192d16SAlbert ARIBAUD \(3ADEV\)};
27*27192d16SAlbert ARIBAUD \(3ADEV\)
28*27192d16SAlbert ARIBAUD \(3ADEV\)&qspi0 {
29*27192d16SAlbert ARIBAUD \(3ADEV\)	bus-num = <0>;
30*27192d16SAlbert ARIBAUD \(3ADEV\)	num-cs = <2>;
31*27192d16SAlbert ARIBAUD \(3ADEV\)	status = "okay";
32*27192d16SAlbert ARIBAUD \(3ADEV\)
33*27192d16SAlbert ARIBAUD \(3ADEV\)	qflash0: spi_flash@0 {
34*27192d16SAlbert ARIBAUD \(3ADEV\)		#address-cells = <1>;
35*27192d16SAlbert ARIBAUD \(3ADEV\)		#size-cells = <1>;
36*27192d16SAlbert ARIBAUD \(3ADEV\)		compatible = "spi-flash";
37*27192d16SAlbert ARIBAUD \(3ADEV\)		spi-max-frequency = <108000000>;
38*27192d16SAlbert ARIBAUD \(3ADEV\)		reg = <0>;
39*27192d16SAlbert ARIBAUD \(3ADEV\)	};
40*27192d16SAlbert ARIBAUD \(3ADEV\)
41*27192d16SAlbert ARIBAUD \(3ADEV\)	qflash1: spi_flash@1 {
42*27192d16SAlbert ARIBAUD \(3ADEV\)		#address-cells = <1>;
43*27192d16SAlbert ARIBAUD \(3ADEV\)		#size-cells = <1>;
44*27192d16SAlbert ARIBAUD \(3ADEV\)		compatible = "spi-flash";
45*27192d16SAlbert ARIBAUD \(3ADEV\)		spi-max-frequency = <66000000>;
46*27192d16SAlbert ARIBAUD \(3ADEV\)		reg = <1>;
47*27192d16SAlbert ARIBAUD \(3ADEV\)	};
48*27192d16SAlbert ARIBAUD \(3ADEV\)};
49