xref: /rk3399_rockchip-uboot/arch/arm/dts/armada-cp110-master.dtsi (revision 7c4f91551898fcd3eff9bbdf295a04fac9e2dc3d)
11335483aSStefan Roese/*
21335483aSStefan Roese * Copyright (C) 2016 Marvell Technology Group Ltd.
31335483aSStefan Roese *
41335483aSStefan Roese * This file is dual-licensed: you can use it either under the terms
51335483aSStefan Roese * of the GPLv2 or the X11 license, at your option. Note that this dual
61335483aSStefan Roese * licensing only applies to this file, and not this project as a
71335483aSStefan Roese * whole.
81335483aSStefan Roese *
91335483aSStefan Roese *  a) This library is free software; you can redistribute it and/or
101335483aSStefan Roese *     modify it under the terms of the GNU General Public License as
111335483aSStefan Roese *     published by the Free Software Foundation; either version 2 of the
121335483aSStefan Roese *     License, or (at your option) any later version.
131335483aSStefan Roese *
141335483aSStefan Roese *     This library is distributed in the hope that it will be useful,
151335483aSStefan Roese *     but WITHOUT ANY WARRANTY; without even the implied warranty of
161335483aSStefan Roese *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
171335483aSStefan Roese *     GNU General Public License for more details.
181335483aSStefan Roese *
191335483aSStefan Roese * Or, alternatively,
201335483aSStefan Roese *
211335483aSStefan Roese *  b) Permission is hereby granted, free of charge, to any person
221335483aSStefan Roese *     obtaining a copy of this software and associated documentation
231335483aSStefan Roese *     files (the "Software"), to deal in the Software without
241335483aSStefan Roese *     restriction, including without limitation the rights to use,
251335483aSStefan Roese *     copy, modify, merge, publish, distribute, sublicense, and/or
261335483aSStefan Roese *     sell copies of the Software, and to permit persons to whom the
271335483aSStefan Roese *     Software is furnished to do so, subject to the following
281335483aSStefan Roese *     conditions:
291335483aSStefan Roese *
301335483aSStefan Roese *     The above copyright notice and this permission notice shall be
311335483aSStefan Roese *     included in all copies or substantial portions of the Software.
321335483aSStefan Roese *
331335483aSStefan Roese *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
341335483aSStefan Roese *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
351335483aSStefan Roese *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
361335483aSStefan Roese *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
371335483aSStefan Roese *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
381335483aSStefan Roese *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
391335483aSStefan Roese *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
401335483aSStefan Roese *     OTHER DEALINGS IN THE SOFTWARE.
411335483aSStefan Roese */
421335483aSStefan Roese
431335483aSStefan Roese/*
441335483aSStefan Roese * Device Tree file for Marvell Armada CP110 Master.
451335483aSStefan Roese */
461335483aSStefan Roese
4778806891SStefan Roese#include <dt-bindings/comphy/comphy_data.h>
4878806891SStefan Roese
491335483aSStefan Roese/ {
501335483aSStefan Roese	cp110-master {
511335483aSStefan Roese		#address-cells = <2>;
521335483aSStefan Roese		#size-cells = <2>;
531335483aSStefan Roese		compatible = "simple-bus";
541335483aSStefan Roese		interrupt-parent = <&gic>;
551335483aSStefan Roese		ranges;
561335483aSStefan Roese
571335483aSStefan Roese		config-space {
581335483aSStefan Roese			#address-cells = <1>;
591335483aSStefan Roese			#size-cells = <1>;
601335483aSStefan Roese			compatible = "simple-bus";
611335483aSStefan Roese			interrupt-parent = <&gic>;
621335483aSStefan Roese			ranges = <0x0 0x0 0xf2000000 0x2000000>;
631335483aSStefan Roese
641335483aSStefan Roese			cpm_syscon0: system-controller@440000 {
651335483aSStefan Roese				compatible = "marvell,cp110-system-controller0",
661335483aSStefan Roese					     "syscon";
671335483aSStefan Roese				reg = <0x440000 0x1000>;
681335483aSStefan Roese				#clock-cells = <2>;
691335483aSStefan Roese				core-clock-output-names =
701335483aSStefan Roese					"cpm-apll", "cpm-ppv2-core", "cpm-eip",
711335483aSStefan Roese					"cpm-core", "cpm-nand-core";
721335483aSStefan Roese				gate-clock-output-names =
731335483aSStefan Roese					"cpm-audio", "cpm-communit", "cpm-nand",
741335483aSStefan Roese					"cpm-ppv2", "cpm-sdio", "cpm-mg-domain",
751335483aSStefan Roese					"cpm-mg-core", "cpm-xor1", "cpm-xor0",
761335483aSStefan Roese					"cpm-gop-dp", "none", "cpm-pcie_x10",
771335483aSStefan Roese					"cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor",
781335483aSStefan Roese					"cpm-sata", "cpm-sata-usb", "cpm-main",
791335483aSStefan Roese					"cpm-sd-mmc", "none", "none",
801335483aSStefan Roese					"cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1",
811335483aSStefan Roese					"cpm-usb3dev", "cpm-eip150", "cpm-eip197";
821335483aSStefan Roese			};
831335483aSStefan Roese
84f99386c5SKonstantin Porotchkin			cpm_pinctl: cpm-pinctl@440000 {
85f99386c5SKonstantin Porotchkin				compatible = "marvell,mvebu-pinctrl",
86f99386c5SKonstantin Porotchkin					     "marvell,a70x0-pinctrl",
87f99386c5SKonstantin Porotchkin					     "marvell,a80x0-cp0-pinctrl";
88f99386c5SKonstantin Porotchkin				bank-name ="cp0-110";
89f99386c5SKonstantin Porotchkin				reg = <0x440000 0x20>;
90f99386c5SKonstantin Porotchkin				pin-count = <63>;
91f99386c5SKonstantin Porotchkin				max-func = <0xf>;
92f99386c5SKonstantin Porotchkin
93f99386c5SKonstantin Porotchkin				cpm_i2c0_pins: cpm-i2c-pins-0 {
94f99386c5SKonstantin Porotchkin					marvell,pins = < 37 38 >;
95f99386c5SKonstantin Porotchkin					marvell,function = <2>;
96f99386c5SKonstantin Porotchkin				};
97*7c4f9155SKonstantin Porotchkin				cpm_i2c1_pins: cpm-i2c-pins-1 {
98*7c4f9155SKonstantin Porotchkin					marvell,pins = < 35 36 >;
99*7c4f9155SKonstantin Porotchkin					marvell,function = <2>;
100*7c4f9155SKonstantin Porotchkin				};
101f99386c5SKonstantin Porotchkin				cpm_ge2_rgmii_pins: cpm-ge-rgmii-pins-0 {
102f99386c5SKonstantin Porotchkin					marvell,pins = < 44 45 46 47 48 49 50 51
103f99386c5SKonstantin Porotchkin							 52 53 54 55 >;
104f99386c5SKonstantin Porotchkin					marvell,function = <1>;
105f99386c5SKonstantin Porotchkin				};
106f99386c5SKonstantin Porotchkin				pca0_pins: cpm-pca0_pins {
107f99386c5SKonstantin Porotchkin					marvell,pins = <62>;
108f99386c5SKonstantin Porotchkin					marvell,function = <0>;
109f99386c5SKonstantin Porotchkin				};
110f99386c5SKonstantin Porotchkin				cpm_sdhci_pins: cpm-sdhi-pins-0 {
111f99386c5SKonstantin Porotchkin					marvell,pins = < 56 57 58 59 60 61 >;
112f99386c5SKonstantin Porotchkin					marvell,function = <14>;
113f99386c5SKonstantin Porotchkin				};
114f99386c5SKonstantin Porotchkin				cpm_spi0_pins: cpm-spi-pins-0 {
115f99386c5SKonstantin Porotchkin					marvell,pins = < 13 14 15 16 >;
116f99386c5SKonstantin Porotchkin					marvell,function = <3>;
117f99386c5SKonstantin Porotchkin				};
118f99386c5SKonstantin Porotchkin			};
119f99386c5SKonstantin Porotchkin
120995a9f42SKonstantin Porotchkin			cpm_gpio0: gpio@440100 {
121995a9f42SKonstantin Porotchkin				compatible = "marvell,orion-gpio";
122995a9f42SKonstantin Porotchkin				reg = <0x440100 0x40>;
123995a9f42SKonstantin Porotchkin				ngpios = <32>;
124995a9f42SKonstantin Porotchkin				gpiobase = <20>;
125995a9f42SKonstantin Porotchkin				gpio-controller;
126995a9f42SKonstantin Porotchkin				#gpio-cells = <2>;
127995a9f42SKonstantin Porotchkin			};
128995a9f42SKonstantin Porotchkin
129995a9f42SKonstantin Porotchkin			cpm_gpio1: gpio@440140 {
130995a9f42SKonstantin Porotchkin				compatible = "marvell,orion-gpio";
131995a9f42SKonstantin Porotchkin				reg = <0x440140 0x40>;
132995a9f42SKonstantin Porotchkin				ngpios = <31>;
133995a9f42SKonstantin Porotchkin				gpiobase = <52>;
134995a9f42SKonstantin Porotchkin				gpio-controller;
135995a9f42SKonstantin Porotchkin				#gpio-cells = <2>;
136995a9f42SKonstantin Porotchkin			};
137995a9f42SKonstantin Porotchkin
1381335483aSStefan Roese			cpm_sata0: sata@540000 {
1391335483aSStefan Roese				compatible = "marvell,armada-8k-ahci";
1401335483aSStefan Roese				reg = <0x540000 0x30000>;
1411335483aSStefan Roese				interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1421335483aSStefan Roese				clocks = <&cpm_syscon0 1 15>;
1431335483aSStefan Roese				status = "disabled";
1441335483aSStefan Roese			};
1451335483aSStefan Roese
1461335483aSStefan Roese			cpm_usb3_0: usb3@500000 {
1471335483aSStefan Roese				compatible = "marvell,armada-8k-xhci",
1481335483aSStefan Roese					     "generic-xhci";
1491335483aSStefan Roese				reg = <0x500000 0x4000>;
1501335483aSStefan Roese				dma-coherent;
1511335483aSStefan Roese				interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1521335483aSStefan Roese				clocks = <&cpm_syscon0 1 22>;
1531335483aSStefan Roese				status = "disabled";
1541335483aSStefan Roese			};
1551335483aSStefan Roese
1561335483aSStefan Roese			cpm_usb3_1: usb3@510000 {
1571335483aSStefan Roese				compatible = "marvell,armada-8k-xhci",
1581335483aSStefan Roese					     "generic-xhci";
1591335483aSStefan Roese				reg = <0x510000 0x4000>;
1601335483aSStefan Roese				dma-coherent;
1611335483aSStefan Roese				interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1621335483aSStefan Roese				clocks = <&cpm_syscon0 1 23>;
1631335483aSStefan Roese				status = "disabled";
1641335483aSStefan Roese			};
1651335483aSStefan Roese
1661335483aSStefan Roese			cpm_spi0: spi@700600 {
1671335483aSStefan Roese				compatible = "marvell,armada-380-spi";
1681335483aSStefan Roese				reg = <0x700600 0x50>;
1691335483aSStefan Roese				#address-cells = <0x1>;
1701335483aSStefan Roese				#size-cells = <0x0>;
1711335483aSStefan Roese				cell-index = <1>;
1721335483aSStefan Roese				clocks = <&cpm_syscon0 0 3>;
1731335483aSStefan Roese				status = "disabled";
1741335483aSStefan Roese			};
1751335483aSStefan Roese
1761335483aSStefan Roese			cpm_spi1: spi@700680 {
1771335483aSStefan Roese				compatible = "marvell,armada-380-spi";
1781335483aSStefan Roese				reg = <0x700680 0x50>;
1791335483aSStefan Roese				#address-cells = <1>;
1801335483aSStefan Roese				#size-cells = <0>;
1811335483aSStefan Roese				cell-index = <2>;
1821335483aSStefan Roese				clocks = <&cpm_syscon0 1 21>;
1831335483aSStefan Roese				status = "disabled";
1841335483aSStefan Roese			};
1851335483aSStefan Roese
1861335483aSStefan Roese			cpm_i2c0: i2c@701000 {
1871335483aSStefan Roese				compatible = "marvell,mv78230-i2c";
1881335483aSStefan Roese				reg = <0x701000 0x20>;
1891335483aSStefan Roese				#address-cells = <1>;
1901335483aSStefan Roese				#size-cells = <0>;
1911335483aSStefan Roese				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1921335483aSStefan Roese				clocks = <&cpm_syscon0 1 21>;
1931335483aSStefan Roese				status = "disabled";
1941335483aSStefan Roese			};
1951335483aSStefan Roese
1961335483aSStefan Roese			cpm_i2c1: i2c@701100 {
1971335483aSStefan Roese				compatible = "marvell,mv78230-i2c";
1981335483aSStefan Roese				reg = <0x701100 0x20>;
1991335483aSStefan Roese				#address-cells = <1>;
2001335483aSStefan Roese				#size-cells = <0>;
2011335483aSStefan Roese				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
2021335483aSStefan Roese				clocks = <&cpm_syscon0 1 21>;
2031335483aSStefan Roese				status = "disabled";
2041335483aSStefan Roese			};
20578806891SStefan Roese
206a12c92e3SStefan Roese			cpm_comphy: comphy@441000 {
20778806891SStefan Roese				compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
20878806891SStefan Roese				reg = <0x441000 0x8>,
20978806891SStefan Roese				      <0x120000 0x8>;
21078806891SStefan Roese				mux-bitcount = <4>;
21178806891SStefan Roese				max-lanes = <6>;
21278806891SStefan Roese			};
21378806891SStefan Roese
214a12c92e3SStefan Roese			cpm_utmi0: utmi@580000 {
21578806891SStefan Roese				compatible = "marvell,mvebu-utmi-2.6.0";
21678806891SStefan Roese				reg = <0x580000 0x1000>,	/* utmi-unit */
21778806891SStefan Roese				      <0x440420 0x4>,		/* usb-cfg */
21878806891SStefan Roese				      <0x440440 0x4>;		/* utmi-cfg */
21978806891SStefan Roese				utmi-port = <UTMI_PHY_TO_USB_HOST0>;
22078806891SStefan Roese				status = "disabled";
22178806891SStefan Roese			};
22278806891SStefan Roese
223a12c92e3SStefan Roese			cpm_utmi1: utmi@581000 {
22478806891SStefan Roese				compatible = "marvell,mvebu-utmi-2.6.0";
22578806891SStefan Roese				reg = <0x581000 0x1000>,	/* utmi-unit */
22678806891SStefan Roese				      <0x440420 0x4>,		/* usb-cfg */
22778806891SStefan Roese				      <0x440444 0x4>;		/* utmi-cfg */
22878806891SStefan Roese				utmi-port = <UTMI_PHY_TO_USB_HOST1>;
22978806891SStefan Roese				status = "disabled";
23078806891SStefan Roese			};
231b14b0b1eSStefan Roese
232b14b0b1eSStefan Roese			cpm_sdhci0: sdhci@780000 {
233b14b0b1eSStefan Roese				compatible = "marvell,armada-8k-sdhci";
234b14b0b1eSStefan Roese				reg = <0x780000 0x300>;
235b14b0b1eSStefan Roese				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
236b14b0b1eSStefan Roese				dma-coherent;
237b14b0b1eSStefan Roese				status = "disabled";
238b14b0b1eSStefan Roese			};
2391335483aSStefan Roese		};
2401335483aSStefan Roese
2411335483aSStefan Roese		cpm_pcie0: pcie@f2600000 {
2421335483aSStefan Roese			compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
2431335483aSStefan Roese			reg = <0 0xf2600000 0 0x10000>,
2441335483aSStefan Roese			      <0 0xf6f00000 0 0x80000>;
2451335483aSStefan Roese			reg-names = "ctrl", "config";
2461335483aSStefan Roese			#address-cells = <3>;
2471335483aSStefan Roese			#size-cells = <2>;
2481335483aSStefan Roese			#interrupt-cells = <1>;
2491335483aSStefan Roese			device_type = "pci";
2501335483aSStefan Roese			dma-coherent;
2511335483aSStefan Roese
2521335483aSStefan Roese			bus-range = <0 0xff>;
2531335483aSStefan Roese			ranges =
2541335483aSStefan Roese				/* downstream I/O */
2551335483aSStefan Roese				<0x81000000 0 0xf9000000 0  0xf9000000 0 0x10000
2561335483aSStefan Roese				/* non-prefetchable memory */
2571335483aSStefan Roese				0x82000000 0 0xf6000000 0  0xf6000000 0 0xf00000>;
2581335483aSStefan Roese			interrupt-map-mask = <0 0 0 0>;
2591335483aSStefan Roese			interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
2601335483aSStefan Roese			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
2611335483aSStefan Roese			num-lanes = <1>;
2621335483aSStefan Roese			clocks = <&cpm_syscon0 1 13>;
2631335483aSStefan Roese			status = "disabled";
2641335483aSStefan Roese		};
2651335483aSStefan Roese
2661335483aSStefan Roese		cpm_pcie1: pcie@f2620000 {
2671335483aSStefan Roese			compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
2681335483aSStefan Roese			reg = <0 0xf2620000 0 0x10000>,
2691335483aSStefan Roese			      <0 0xf7f00000 0 0x80000>;
2701335483aSStefan Roese			reg-names = "ctrl", "config";
2711335483aSStefan Roese			#address-cells = <3>;
2721335483aSStefan Roese			#size-cells = <2>;
2731335483aSStefan Roese			#interrupt-cells = <1>;
2741335483aSStefan Roese			device_type = "pci";
2751335483aSStefan Roese			dma-coherent;
2761335483aSStefan Roese
2771335483aSStefan Roese			bus-range = <0 0xff>;
2781335483aSStefan Roese			ranges =
2791335483aSStefan Roese				/* downstream I/O */
2801335483aSStefan Roese				<0x81000000 0 0xf9010000 0  0xf9010000 0 0x10000
2811335483aSStefan Roese				/* non-prefetchable memory */
2821335483aSStefan Roese				0x82000000 0 0xf7000000 0  0xf7000000 0 0xf00000>;
2831335483aSStefan Roese			interrupt-map-mask = <0 0 0 0>;
2841335483aSStefan Roese			interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
2851335483aSStefan Roese			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
2861335483aSStefan Roese
2871335483aSStefan Roese			num-lanes = <1>;
2881335483aSStefan Roese			clocks = <&cpm_syscon0 1 11>;
2891335483aSStefan Roese			status = "disabled";
2901335483aSStefan Roese		};
2911335483aSStefan Roese
2921335483aSStefan Roese		cpm_pcie2: pcie@f2640000 {
2931335483aSStefan Roese			compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
2941335483aSStefan Roese			reg = <0 0xf2640000 0 0x10000>,
2951335483aSStefan Roese			      <0 0xf8f00000 0 0x80000>;
2961335483aSStefan Roese			reg-names = "ctrl", "config";
2971335483aSStefan Roese			#address-cells = <3>;
2981335483aSStefan Roese			#size-cells = <2>;
2991335483aSStefan Roese			#interrupt-cells = <1>;
3001335483aSStefan Roese			device_type = "pci";
3011335483aSStefan Roese			dma-coherent;
3021335483aSStefan Roese
3031335483aSStefan Roese			bus-range = <0 0xff>;
3041335483aSStefan Roese			ranges =
3051335483aSStefan Roese				/* downstream I/O */
3061335483aSStefan Roese				<0x81000000 0 0xf9020000 0  0xf9020000 0 0x10000
3071335483aSStefan Roese				/* non-prefetchable memory */
3081335483aSStefan Roese				0x82000000 0 0xf8000000 0  0xf8000000 0 0xf00000>;
3091335483aSStefan Roese			interrupt-map-mask = <0 0 0 0>;
3101335483aSStefan Roese			interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3111335483aSStefan Roese			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3121335483aSStefan Roese
3131335483aSStefan Roese			num-lanes = <1>;
3141335483aSStefan Roese			clocks = <&cpm_syscon0 1 12>;
3151335483aSStefan Roese			status = "disabled";
3161335483aSStefan Roese		};
3171335483aSStefan Roese	};
3181335483aSStefan Roese};
319