xref: /rk3399_rockchip-uboot/arch/arm/dts/armada-385-amc.dts (revision 4109d702934c361b2ae2a5ad34f4dfee708cc214)
1c0def248SChris Packham/*
2c0def248SChris Packham * Device Tree file for Marvell Armada 385 development board
3c0def248SChris Packham * (DB-88F6820-AMC)
4c0def248SChris Packham *
5c0def248SChris Packham * Copyright (C) 2014 Marvell
6c0def248SChris Packham *
7c0def248SChris Packham * Gregory CLEMENT <gregory.clement@free-electrons.com>
8c0def248SChris Packham *
9c0def248SChris Packham * This file is dual-licensed: you can use it either under the terms
10c0def248SChris Packham * of the GPL or the X11 license, at your option. Note that this dual
11c0def248SChris Packham * licensing only applies to this file, and not this project as a
12c0def248SChris Packham * whole.
13c0def248SChris Packham *
14c0def248SChris Packham *  a) This file is licensed under the terms of the GNU General Public
15c0def248SChris Packham *     License version 2.  This program is licensed "as is" without
16c0def248SChris Packham *     any warranty of any kind, whether express or implied.
17c0def248SChris Packham *
18c0def248SChris Packham * Or, alternatively,
19c0def248SChris Packham *
20c0def248SChris Packham *  b) Permission is hereby granted, free of charge, to any person
21c0def248SChris Packham *     obtaining a copy of this software and associated documentation
22c0def248SChris Packham *     files (the "Software"), to deal in the Software without
23c0def248SChris Packham *     restriction, including without limitation the rights to use,
24c0def248SChris Packham *     copy, modify, merge, publish, distribute, sublicense, and/or
25c0def248SChris Packham *     sell copies of the Software, and to permit persons to whom the
26c0def248SChris Packham *     Software is furnished to do so, subject to the following
27c0def248SChris Packham *     conditions:
28c0def248SChris Packham *
29c0def248SChris Packham *     The above copyright notice and this permission notice shall be
30c0def248SChris Packham *     included in all copies or substantial portions of the Software.
31c0def248SChris Packham *
32c0def248SChris Packham *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33c0def248SChris Packham *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34c0def248SChris Packham *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35c0def248SChris Packham *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36c0def248SChris Packham *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37c0def248SChris Packham *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38c0def248SChris Packham *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39c0def248SChris Packham *     OTHER DEALINGS IN THE SOFTWARE.
40c0def248SChris Packham */
41c0def248SChris Packham
42c0def248SChris Packham/dts-v1/;
43c0def248SChris Packham#include "armada-385.dtsi"
44c0def248SChris Packham#include <dt-bindings/gpio/gpio.h>
45c0def248SChris Packham
46c0def248SChris Packham/ {
47c0def248SChris Packham	model = "Marvell Armada 385 AMC";
48c0def248SChris Packham	compatible = "marvell,a385-amc", "marvell,armada385", "marvell,armada380";
49c0def248SChris Packham
50c0def248SChris Packham	chosen {
51c0def248SChris Packham		stdout-path = "serial0:115200n8";
52c0def248SChris Packham	};
53c0def248SChris Packham
54c0def248SChris Packham	aliases {
55c0def248SChris Packham		ethernet0 = &eth0;
56c0def248SChris Packham		ethernet1 = &eth1;
57e38f5fc8SChris Packham		i2c0 = &i2c0;
58c0def248SChris Packham		spi1 = &spi1;
59c0def248SChris Packham	};
60c0def248SChris Packham
61c0def248SChris Packham	memory {
62c0def248SChris Packham		device_type = "memory";
63c0def248SChris Packham		reg = <0x00000000 0x80000000>; /* 2 GB */
64c0def248SChris Packham	};
65c0def248SChris Packham
66c0def248SChris Packham	soc {
67c0def248SChris Packham		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
68c0def248SChris Packham			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
69c0def248SChris Packham
70c0def248SChris Packham		internal-regs {
71c0def248SChris Packham			i2c@11000 {
72e38f5fc8SChris Packham				clock-frequency = <100000>;
73e38f5fc8SChris Packham				u-boot,i2c-slave-addr = <0x0>;
74c0def248SChris Packham				pinctrl-names = "default";
75c0def248SChris Packham				pinctrl-0 = <&i2c0_pins>;
76c0def248SChris Packham				status = "okay";
77c0def248SChris Packham			};
78c0def248SChris Packham
79c0def248SChris Packham			serial@12000 {
80c0def248SChris Packham				/*
81c0def248SChris Packham				 * Exported on the micro USB connector CON16
82c0def248SChris Packham				 * through an FTDI
83c0def248SChris Packham				 */
84c0def248SChris Packham
85c0def248SChris Packham				pinctrl-names = "default";
86c0def248SChris Packham				pinctrl-0 = <&uart0_pins>;
87c0def248SChris Packham				status = "okay";
88c0def248SChris Packham				u-boot,dm-pre-reloc;
89c0def248SChris Packham			};
90c0def248SChris Packham
91c0def248SChris Packham			ethernet@34000 {
92c0def248SChris Packham				status = "okay";
93c0def248SChris Packham				phy = <&phy1>;
94c0def248SChris Packham				phy-mode = "sgmii";
95c0def248SChris Packham			};
96c0def248SChris Packham
97c0def248SChris Packham			usb@58000 {
98c0def248SChris Packham				status = "okay";
99c0def248SChris Packham			};
100c0def248SChris Packham
101c0def248SChris Packham			ethernet@70000 {
102c0def248SChris Packham				pinctrl-names = "default";
103c0def248SChris Packham				/*
104c0def248SChris Packham				 * The Reference Clock 0 is used to provide a
105c0def248SChris Packham				 * clock to the PHY
106c0def248SChris Packham				 */
107c0def248SChris Packham				pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
108c0def248SChris Packham				status = "okay";
109c0def248SChris Packham				phy = <&phy0>;
110c0def248SChris Packham				phy-mode = "rgmii-id";
111c0def248SChris Packham			};
112c0def248SChris Packham
113c0def248SChris Packham
114c0def248SChris Packham			mdio@72004 {
115c0def248SChris Packham				pinctrl-names = "default";
116c0def248SChris Packham				pinctrl-0 = <&mdio_pins>;
117c0def248SChris Packham
118c0def248SChris Packham				phy0: ethernet-phy@1 {
119c0def248SChris Packham					reg = <1>;
120c0def248SChris Packham				};
121c0def248SChris Packham
122c0def248SChris Packham				phy1: ethernet-phy@0 {
123c0def248SChris Packham					reg = <0>;
124c0def248SChris Packham				};
125c0def248SChris Packham			};
12642f75050SChris Packham
12742f75050SChris Packham			flash@d0000 {
12842f75050SChris Packham				status = "okay";
12942f75050SChris Packham				num-cs = <1>;
13042f75050SChris Packham				marvell,nand-keep-config;
13142f75050SChris Packham				marvell,nand-enable-arbiter;
13242f75050SChris Packham				nand-on-flash-bbt;
13342f75050SChris Packham			};
134c0def248SChris Packham		};
135c0def248SChris Packham
136c0def248SChris Packham		pcie-controller {
137c0def248SChris Packham			status = "okay";
138c0def248SChris Packham			pcie@1,0 {
139c0def248SChris Packham				/* Port 0, Lane 0 */
140c0def248SChris Packham				status = "okay";
141c0def248SChris Packham			};
142c0def248SChris Packham
143c0def248SChris Packham		};
144c0def248SChris Packham	};
145c0def248SChris Packham};
146c0def248SChris Packham
147c0def248SChris Packham&spi1 {
148c0def248SChris Packham	pinctrl-names = "default";
149c0def248SChris Packham	pinctrl-0 = <&spi1_pins>;
150c0def248SChris Packham	status = "okay";
151c0def248SChris Packham	u-boot,dm-pre-reloc;
152c0def248SChris Packham
153c0def248SChris Packham	spi-flash@0 {
154c0def248SChris Packham		u-boot,dm-pre-reloc;
155c0def248SChris Packham		#address-cells = <1>;
156c0def248SChris Packham		#size-cells = <1>;
157*dbc3e64fSChris Packham		compatible = "st,m25p128", "jedec,spi-nor", "spi-flash";
158c0def248SChris Packham		reg = <0>; /* Chip select 0 */
159c0def248SChris Packham		spi-max-frequency = <50000000>;
160c0def248SChris Packham		m25p,fast-read;
161c0def248SChris Packham	};
162c0def248SChris Packham};
163c0def248SChris Packham
164c0def248SChris Packham&refclk {
165c0def248SChris Packham	clock-frequency = <20000000>;
166c0def248SChris Packham};
167