1dde3b70dSSimon Glass/* 2dde3b70dSSimon Glass * Copyright (c) 2004-2008 Texas Instruments 3dde3b70dSSimon Glass * 4dde3b70dSSimon Glass * (C) Copyright 2002 5dde3b70dSSimon Glass * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> 6dde3b70dSSimon Glass * 71a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 8dde3b70dSSimon Glass */ 9dde3b70dSSimon Glass 10bf433afdSMarc Zyngier#include <config.h> 11980d6a55SChen-Yu Tsai#include <asm/psci.h> 12bf433afdSMarc Zyngier 13dde3b70dSSimon GlassOUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") 14dde3b70dSSimon GlassOUTPUT_ARCH(arm) 15dde3b70dSSimon GlassENTRY(_start) 16dde3b70dSSimon GlassSECTIONS 17dde3b70dSSimon Glass{ 18c1352119SSimon Glass#ifndef CONFIG_CMDLINE 19c1352119SSimon Glass /DISCARD/ : { *(.u_boot_list_2_cmd_*) } 20c1352119SSimon Glass#endif 21c5e954ecSWang Dongsheng#if defined(CONFIG_ARMV7_SECURE_BASE) && defined(CONFIG_ARMV7_NONSEC) 22d47cb0b6SPeng Fan /* 23c5e954ecSWang Dongsheng * If CONFIG_ARMV7_SECURE_BASE is true, secure code will not 24c5e954ecSWang Dongsheng * bundle with u-boot, and code offsets are fixed. Secure zone 25c5e954ecSWang Dongsheng * only needs to be copied from the loading address to 26c5e954ecSWang Dongsheng * CONFIG_ARMV7_SECURE_BASE, which is the linking and running 27c5e954ecSWang Dongsheng * address for secure code. 28d47cb0b6SPeng Fan * 29c5e954ecSWang Dongsheng * If CONFIG_ARMV7_SECURE_BASE is undefined, the secure zone will 30c5e954ecSWang Dongsheng * be included in u-boot address space, and some absolute address 31c5e954ecSWang Dongsheng * were used in secure code. The absolute addresses of the secure 32c5e954ecSWang Dongsheng * code also needs to be relocated along with the accompanying u-boot 33c5e954ecSWang Dongsheng * code. 34c5e954ecSWang Dongsheng * 35c5e954ecSWang Dongsheng * So DISCARD is only for CONFIG_ARMV7_SECURE_BASE. 36d47cb0b6SPeng Fan */ 37d47cb0b6SPeng Fan /DISCARD/ : { *(.rel._secure*) } 38c5e954ecSWang Dongsheng#endif 39dde3b70dSSimon Glass . = 0x00000000; 40dde3b70dSSimon Glass 41dde3b70dSSimon Glass . = ALIGN(4); 42dde3b70dSSimon Glass .text : 43dde3b70dSSimon Glass { 44d026dec8SAlbert ARIBAUD *(.__image_copy_start) 4541623c91SAlbert ARIBAUD *(.vectors) 46b68d6712SStephen Warren CPUDIR/start.o (.text*) 47b68d6712SStephen Warren *(.text*) 48dde3b70dSSimon Glass } 49dde3b70dSSimon Glass 50104d6fb6SJan Kiszka#ifdef CONFIG_ARMV7_NONSEC 51bf433afdSMarc Zyngier 52a1274cc9SChen-Yu Tsai /* Align the secure section only if we're going to use it in situ */ 53a1274cc9SChen-Yu Tsai .__secure_start : 54a1274cc9SChen-Yu Tsai#ifndef CONFIG_ARMV7_SECURE_BASE 55a1274cc9SChen-Yu Tsai ALIGN(CONSTANT(COMMONPAGESIZE)) 56a1274cc9SChen-Yu Tsai#endif 57a1274cc9SChen-Yu Tsai { 58a1274cc9SChen-Yu Tsai KEEP(*(.__secure_start)) 59a1274cc9SChen-Yu Tsai } 60a1274cc9SChen-Yu Tsai 61bf433afdSMarc Zyngier#ifndef CONFIG_ARMV7_SECURE_BASE 62bf433afdSMarc Zyngier#define CONFIG_ARMV7_SECURE_BASE 63b56e06d3SChen-Yu Tsai#define __ARMV7_PSCI_STACK_IN_RAM 64bf433afdSMarc Zyngier#endif 65bf433afdSMarc Zyngier 66bf433afdSMarc Zyngier .secure_text CONFIG_ARMV7_SECURE_BASE : 67bf433afdSMarc Zyngier AT(ADDR(.__secure_start) + SIZEOF(.__secure_start)) 68bf433afdSMarc Zyngier { 69bf433afdSMarc Zyngier *(._secure.text) 70bf433afdSMarc Zyngier } 71bf433afdSMarc Zyngier 72*a5aa7ff3SChen-Yu Tsai .secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text)) 73*a5aa7ff3SChen-Yu Tsai { 74*a5aa7ff3SChen-Yu Tsai *(._secure.data) 75*a5aa7ff3SChen-Yu Tsai } 76*a5aa7ff3SChen-Yu Tsai 77*a5aa7ff3SChen-Yu Tsai .secure_stack ALIGN(ADDR(.secure_data) + SIZEOF(.secure_data), 78980d6a55SChen-Yu Tsai CONSTANT(COMMONPAGESIZE)) (NOLOAD) : 79b56e06d3SChen-Yu Tsai#ifdef __ARMV7_PSCI_STACK_IN_RAM 80980d6a55SChen-Yu Tsai AT(ADDR(.secure_stack)) 81980d6a55SChen-Yu Tsai#else 82*a5aa7ff3SChen-Yu Tsai AT(LOADADDR(.secure_data) + SIZEOF(.secure_data)) 83980d6a55SChen-Yu Tsai#endif 84980d6a55SChen-Yu Tsai { 85980d6a55SChen-Yu Tsai KEEP(*(.__secure_stack_start)) 86980d6a55SChen-Yu Tsai 87980d6a55SChen-Yu Tsai /* Skip addreses for stack */ 88980d6a55SChen-Yu Tsai . = . + CONFIG_ARMV7_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE; 89980d6a55SChen-Yu Tsai 90980d6a55SChen-Yu Tsai /* Align end of stack section to page boundary */ 91980d6a55SChen-Yu Tsai . = ALIGN(CONSTANT(COMMONPAGESIZE)); 92980d6a55SChen-Yu Tsai 93980d6a55SChen-Yu Tsai KEEP(*(.__secure_stack_end)) 943eff6818SChen-Yu Tsai 953eff6818SChen-Yu Tsai#ifdef CONFIG_ARMV7_SECURE_MAX_SIZE 963eff6818SChen-Yu Tsai /* 973eff6818SChen-Yu Tsai * We are not checking (__secure_end - __secure_start) here, 983eff6818SChen-Yu Tsai * as these are the load addresses, and do not include the 993eff6818SChen-Yu Tsai * stack section. Instead, use the end of the stack section 1003eff6818SChen-Yu Tsai * and the start of the text section. 1013eff6818SChen-Yu Tsai */ 1023eff6818SChen-Yu Tsai ASSERT((. - ADDR(.secure_text)) <= CONFIG_ARMV7_SECURE_MAX_SIZE, 1033eff6818SChen-Yu Tsai "Error: secure section exceeds secure memory size"); 1043eff6818SChen-Yu Tsai#endif 105980d6a55SChen-Yu Tsai } 106980d6a55SChen-Yu Tsai 107980d6a55SChen-Yu Tsai#ifndef __ARMV7_PSCI_STACK_IN_RAM 108980d6a55SChen-Yu Tsai /* Reset VMA but don't allocate space if we have secure SRAM */ 109980d6a55SChen-Yu Tsai . = LOADADDR(.secure_stack); 110b56e06d3SChen-Yu Tsai#endif 111b56e06d3SChen-Yu Tsai 112980d6a55SChen-Yu Tsai .__secure_end : AT(ADDR(.__secure_end)) { 113bf433afdSMarc Zyngier *(.__secure_end) 114bf433afdSMarc Zyngier LONG(0x1d1071c); /* Must output something to reset LMA */ 115bf433afdSMarc Zyngier } 116bf433afdSMarc Zyngier#endif 117bf433afdSMarc Zyngier 118dde3b70dSSimon Glass . = ALIGN(4); 119dde3b70dSSimon Glass .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } 120dde3b70dSSimon Glass 121dde3b70dSSimon Glass . = ALIGN(4); 122dde3b70dSSimon Glass .data : { 123b68d6712SStephen Warren *(.data*) 124dde3b70dSSimon Glass } 125dde3b70dSSimon Glass 126dde3b70dSSimon Glass . = ALIGN(4); 127dde3b70dSSimon Glass 128dde3b70dSSimon Glass . = .; 129dde3b70dSSimon Glass 130dde3b70dSSimon Glass . = ALIGN(4); 13155675142SMarek Vasut .u_boot_list : { 132ef123c52SAlbert ARIBAUD KEEP(*(SORT(.u_boot_list*))); 13355675142SMarek Vasut } 13455675142SMarek Vasut 13555675142SMarek Vasut . = ALIGN(4); 136dde3b70dSSimon Glass 13750149ea3SAlexander Graf .__efi_runtime_start : { 13850149ea3SAlexander Graf *(.__efi_runtime_start) 13950149ea3SAlexander Graf } 14050149ea3SAlexander Graf 14150149ea3SAlexander Graf .efi_runtime : { 14250149ea3SAlexander Graf *(efi_runtime_text) 14350149ea3SAlexander Graf *(efi_runtime_data) 14450149ea3SAlexander Graf } 14550149ea3SAlexander Graf 14650149ea3SAlexander Graf .__efi_runtime_stop : { 14750149ea3SAlexander Graf *(.__efi_runtime_stop) 14850149ea3SAlexander Graf } 14950149ea3SAlexander Graf 15050149ea3SAlexander Graf .efi_runtime_rel_start : 15150149ea3SAlexander Graf { 15250149ea3SAlexander Graf *(.__efi_runtime_rel_start) 15350149ea3SAlexander Graf } 15450149ea3SAlexander Graf 15550149ea3SAlexander Graf .efi_runtime_rel : { 15650149ea3SAlexander Graf *(.relefi_runtime_text) 15750149ea3SAlexander Graf *(.relefi_runtime_data) 15850149ea3SAlexander Graf } 15950149ea3SAlexander Graf 16050149ea3SAlexander Graf .efi_runtime_rel_stop : 16150149ea3SAlexander Graf { 16250149ea3SAlexander Graf *(.__efi_runtime_rel_stop) 16350149ea3SAlexander Graf } 16450149ea3SAlexander Graf 16550149ea3SAlexander Graf . = ALIGN(4); 16650149ea3SAlexander Graf 167d026dec8SAlbert ARIBAUD .image_copy_end : 168d026dec8SAlbert ARIBAUD { 169d026dec8SAlbert ARIBAUD *(.__image_copy_end) 170d026dec8SAlbert ARIBAUD } 171dde3b70dSSimon Glass 17247bd65efSAlbert ARIBAUD .rel_dyn_start : 17347bd65efSAlbert ARIBAUD { 17447bd65efSAlbert ARIBAUD *(.__rel_dyn_start) 17547bd65efSAlbert ARIBAUD } 17647bd65efSAlbert ARIBAUD 177dde3b70dSSimon Glass .rel.dyn : { 178dde3b70dSSimon Glass *(.rel*) 17947bd65efSAlbert ARIBAUD } 18047bd65efSAlbert ARIBAUD 18147bd65efSAlbert ARIBAUD .rel_dyn_end : 18247bd65efSAlbert ARIBAUD { 18347bd65efSAlbert ARIBAUD *(.__rel_dyn_end) 184dde3b70dSSimon Glass } 185dde3b70dSSimon Glass 186d0b5d9daSAlbert ARIBAUD .end : 187d0b5d9daSAlbert ARIBAUD { 188d0b5d9daSAlbert ARIBAUD *(.__end) 189d0b5d9daSAlbert ARIBAUD } 190d0b5d9daSAlbert ARIBAUD 191d0b5d9daSAlbert ARIBAUD _image_binary_end = .; 192dde3b70dSSimon Glass 193dde3b70dSSimon Glass /* 194dde3b70dSSimon Glass * Deprecated: this MMU section is used by pxa at present but 195dde3b70dSSimon Glass * should not be used by new boards/CPUs. 196dde3b70dSSimon Glass */ 197dde3b70dSSimon Glass . = ALIGN(4096); 198dde3b70dSSimon Glass .mmutable : { 199dde3b70dSSimon Glass *(.mmutable) 200dde3b70dSSimon Glass } 201dde3b70dSSimon Glass 202f84a7b8fSAlbert ARIBAUD/* 203f84a7b8fSAlbert ARIBAUD * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c 204f84a7b8fSAlbert ARIBAUD * __bss_base and __bss_limit are for linker only (overlay ordering) 205f84a7b8fSAlbert ARIBAUD */ 206f84a7b8fSAlbert ARIBAUD 2073ebd1cbcSAlbert ARIBAUD .bss_start __rel_dyn_start (OVERLAY) : { 2083ebd1cbcSAlbert ARIBAUD KEEP(*(.__bss_start)); 209f84a7b8fSAlbert ARIBAUD __bss_base = .; 2103ebd1cbcSAlbert ARIBAUD } 2113ebd1cbcSAlbert ARIBAUD 212f84a7b8fSAlbert ARIBAUD .bss __bss_base (OVERLAY) : { 213b68d6712SStephen Warren *(.bss*) 214dde3b70dSSimon Glass . = ALIGN(4); 215f84a7b8fSAlbert ARIBAUD __bss_limit = .; 216dde3b70dSSimon Glass } 217dde3b70dSSimon Glass 218f84a7b8fSAlbert ARIBAUD .bss_end __bss_limit (OVERLAY) : { 219f84a7b8fSAlbert ARIBAUD KEEP(*(.__bss_end)); 220dde3b70dSSimon Glass } 221dde3b70dSSimon Glass 222d0b5d9daSAlbert ARIBAUD .dynsym _image_binary_end : { *(.dynsym) } 22347ed5dd0SAlbert ARIBAUD .dynbss : { *(.dynbss) } 22447ed5dd0SAlbert ARIBAUD .dynstr : { *(.dynstr*) } 22547ed5dd0SAlbert ARIBAUD .dynamic : { *(.dynamic*) } 22647ed5dd0SAlbert ARIBAUD .plt : { *(.plt*) } 22747ed5dd0SAlbert ARIBAUD .interp : { *(.interp*) } 2282c67e0e7SAndreas Färber .gnu.hash : { *(.gnu.hash) } 22947ed5dd0SAlbert ARIBAUD .gnu : { *(.gnu*) } 23047ed5dd0SAlbert ARIBAUD .ARM.exidx : { *(.ARM.exidx*) } 231b02bfc4dSAlbert ARIBAUD .gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) } 232dde3b70dSSimon Glass} 233