xref: /rk3399_rockchip-uboot/arch/arm/cpu/u-boot-spl.lds (revision f8fff9dac9226792491e4106c13ebda985fe4e90)
165cdd643SAlbert ARIBAUD/*
265cdd643SAlbert ARIBAUD * Copyright (c) 2004-2008 Texas Instruments
365cdd643SAlbert ARIBAUD *
465cdd643SAlbert ARIBAUD * (C) Copyright 2002
565cdd643SAlbert ARIBAUD * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
665cdd643SAlbert ARIBAUD *
71a459660SWolfgang Denk * SPDX-License-Identifier:	GPL-2.0+
865cdd643SAlbert ARIBAUD */
965cdd643SAlbert ARIBAUD
1065cdd643SAlbert ARIBAUDOUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
1165cdd643SAlbert ARIBAUDOUTPUT_ARCH(arm)
1265cdd643SAlbert ARIBAUDENTRY(_start)
1365cdd643SAlbert ARIBAUDSECTIONS
1465cdd643SAlbert ARIBAUD{
1565cdd643SAlbert ARIBAUD	. = 0x00000000;
1665cdd643SAlbert ARIBAUD
1765cdd643SAlbert ARIBAUD	. = ALIGN(4);
1865cdd643SAlbert ARIBAUD	.text :
1965cdd643SAlbert ARIBAUD	{
2065cdd643SAlbert ARIBAUD		__image_copy_start = .;
2141623c91SAlbert ARIBAUD		*(.vectors)
2265cdd643SAlbert ARIBAUD		CPUDIR/start.o (.text*)
2365cdd643SAlbert ARIBAUD		*(.text*)
2465cdd643SAlbert ARIBAUD	}
2565cdd643SAlbert ARIBAUD
2665cdd643SAlbert ARIBAUD	. = ALIGN(4);
2765cdd643SAlbert ARIBAUD	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
2865cdd643SAlbert ARIBAUD
2965cdd643SAlbert ARIBAUD	. = ALIGN(4);
3065cdd643SAlbert ARIBAUD	.data : {
3165cdd643SAlbert ARIBAUD		*(.data*)
3265cdd643SAlbert ARIBAUD	}
3365cdd643SAlbert ARIBAUD
3465cdd643SAlbert ARIBAUD	. = ALIGN(4);
3565cdd643SAlbert ARIBAUD
3665cdd643SAlbert ARIBAUD	. = .;
37*f8fff9daSSimon Glass#ifdef CONFIG_SPL_DM
38*f8fff9daSSimon Glass	.u_boot_list : {
39*f8fff9daSSimon Glass		KEEP(*(SORT(.u_boot_list_*_driver_*)));
40*f8fff9daSSimon Glass		KEEP(*(SORT(.u_boot_list_*_uclass_*)));
41*f8fff9daSSimon Glass	}
42*f8fff9daSSimon Glass#endif
43*f8fff9daSSimon Glass	. = ALIGN(4);
4465cdd643SAlbert ARIBAUD
4565cdd643SAlbert ARIBAUD	__image_copy_end = .;
4665cdd643SAlbert ARIBAUD
4765cdd643SAlbert ARIBAUD	.rel.dyn : {
4865cdd643SAlbert ARIBAUD		__rel_dyn_start = .;
4965cdd643SAlbert ARIBAUD		*(.rel*)
5065cdd643SAlbert ARIBAUD		__rel_dyn_end = .;
5165cdd643SAlbert ARIBAUD	}
5265cdd643SAlbert ARIBAUD
53d0b5d9daSAlbert ARIBAUD	.end :
54d0b5d9daSAlbert ARIBAUD	{
55d0b5d9daSAlbert ARIBAUD		*(.__end)
56d0b5d9daSAlbert ARIBAUD	}
57d0b5d9daSAlbert ARIBAUD
58d0b5d9daSAlbert ARIBAUD	_image_binary_end = .;
5965cdd643SAlbert ARIBAUD
6065cdd643SAlbert ARIBAUD	.bss __rel_dyn_start (OVERLAY) : {
6165cdd643SAlbert ARIBAUD		__bss_start = .;
6265cdd643SAlbert ARIBAUD		*(.bss*)
6365cdd643SAlbert ARIBAUD		 . = ALIGN(4);
640ce033d2STom Rini		__bss_end = .;
6565cdd643SAlbert ARIBAUD	}
6665cdd643SAlbert ARIBAUD
67d0b5d9daSAlbert ARIBAUD	.dynsym _image_binary_end : { *(.dynsym) }
6847ed5dd0SAlbert ARIBAUD	.dynbss : { *(.dynbss) }
6947ed5dd0SAlbert ARIBAUD	.dynstr : { *(.dynstr*) }
7047ed5dd0SAlbert ARIBAUD	.dynamic : { *(.dynamic*) }
7147ed5dd0SAlbert ARIBAUD	.hash : { *(.hash*) }
7247ed5dd0SAlbert ARIBAUD	.plt : { *(.plt*) }
7347ed5dd0SAlbert ARIBAUD	.interp : { *(.interp*) }
7447ed5dd0SAlbert ARIBAUD	.gnu : { *(.gnu*) }
7547ed5dd0SAlbert ARIBAUD	.ARM.exidx : { *(.ARM.exidx*) }
7665cdd643SAlbert ARIBAUD}
7765cdd643SAlbert ARIBAUD
786ebc3461SAlbert ARIBAUD#if defined(CONFIG_SPL_MAX_SIZE)
796ebc3461SAlbert ARIBAUDASSERT(__image_copy_end - __image_copy_start < (CONFIG_SPL_MAX_SIZE), \
806ebc3461SAlbert ARIBAUD	"SPL image too big");
816ebc3461SAlbert ARIBAUD#endif
826ebc3461SAlbert ARIBAUD
836ebc3461SAlbert ARIBAUD#if defined(CONFIG_SPL_BSS_MAX_SIZE)
846ebc3461SAlbert ARIBAUDASSERT(__bss_end - __bss_start < (CONFIG_SPL_BSS_MAX_SIZE), \
856ebc3461SAlbert ARIBAUD	"SPL image BSS too big");
866ebc3461SAlbert ARIBAUD#endif
876ebc3461SAlbert ARIBAUD
886ebc3461SAlbert ARIBAUD#if defined(CONFIG_SPL_MAX_FOOTPRINT)
896ebc3461SAlbert ARIBAUDASSERT(__bss_end - _start < (CONFIG_SPL_MAX_FOOTPRINT), \
906ebc3461SAlbert ARIBAUD	"SPL image plus BSS too big");
9165cdd643SAlbert ARIBAUD#endif
92