1/* 2 * armboot - Startup Code for SA1100 CPU 3 * 4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> 7 * Copyright (c) 2001 Alex Züpke <azu@sysgo.de> 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28#include <asm-offsets.h> 29#include <config.h> 30#include <version.h> 31 32/* 33 ************************************************************************* 34 * 35 * Jump vector table as in table 3.1 in [1] 36 * 37 ************************************************************************* 38 */ 39 40 41.globl _start 42_start: b reset 43 ldr pc, _undefined_instruction 44 ldr pc, _software_interrupt 45 ldr pc, _prefetch_abort 46 ldr pc, _data_abort 47 ldr pc, _not_used 48 ldr pc, _irq 49 ldr pc, _fiq 50 51_undefined_instruction: .word undefined_instruction 52_software_interrupt: .word software_interrupt 53_prefetch_abort: .word prefetch_abort 54_data_abort: .word data_abort 55_not_used: .word not_used 56_irq: .word irq 57_fiq: .word fiq 58 59 .balignl 16,0xdeadbeef 60 61 62/* 63 ************************************************************************* 64 * 65 * Startup Code (reset vector) 66 * 67 * do important init only if we don't start from memory! 68 * relocate armboot to ram 69 * setup stack 70 * jump to second stage 71 * 72 ************************************************************************* 73 */ 74 75.globl _TEXT_BASE 76_TEXT_BASE: 77#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) 78 .word CONFIG_SPL_TEXT_BASE 79#else 80 .word CONFIG_SYS_TEXT_BASE 81#endif 82 83/* 84 * These are defined in the board-specific linker script. 85 * Subtracting _start from them lets the linker put their 86 * relative position in the executable instead of leaving 87 * them null. 88 */ 89.globl _bss_start_ofs 90_bss_start_ofs: 91 .word __bss_start - _start 92 93.globl _bss_end_ofs 94_bss_end_ofs: 95 .word __bss_end - _start 96 97.globl _end_ofs 98_end_ofs: 99 .word _end - _start 100 101#ifdef CONFIG_USE_IRQ 102/* IRQ stack memory (calculated at run-time) */ 103.globl IRQ_STACK_START 104IRQ_STACK_START: 105 .word 0x0badc0de 106 107/* IRQ stack memory (calculated at run-time) */ 108.globl FIQ_STACK_START 109FIQ_STACK_START: 110 .word 0x0badc0de 111#endif 112 113/* IRQ stack memory (calculated at run-time) + 8 bytes */ 114.globl IRQ_STACK_START_IN 115IRQ_STACK_START_IN: 116 .word 0x0badc0de 117 118/* 119 * the actual reset code 120 */ 121 122reset: 123 /* 124 * set the cpu to SVC32 mode 125 */ 126 mrs r0,cpsr 127 bic r0,r0,#0x1f 128 orr r0,r0,#0xd3 129 msr cpsr,r0 130 131 /* 132 * we do sys-critical inits only at reboot, 133 * not when booting from ram! 134 */ 135#ifndef CONFIG_SKIP_LOWLEVEL_INIT 136 bl cpu_init_crit 137#endif 138 139 bl _main 140 141/*------------------------------------------------------------------------------*/ 142 143#ifndef CONFIG_SPL_BUILD 144/* 145 * void relocate_code(addr_moni) 146 * 147 * This function relocates the monitor code. 148 */ 149 .globl relocate_code 150relocate_code: 151 mov r6, r0 /* save addr of destination */ 152 153 adr r0, _start 154 subs r9, r6, r0 /* r9 <- relocation offset */ 155 beq relocate_done /* skip relocation */ 156 mov r1, r6 /* r1 <- scratch for copy_loop */ 157 ldr r3, _image_copy_end_ofs 158 add r2, r0, r3 /* r2 <- source end address */ 159 160copy_loop: 161 ldmia r0!, {r10-r11} /* copy from source address [r0] */ 162 stmia r1!, {r10-r11} /* copy to target address [r1] */ 163 cmp r0, r2 /* until source end address [r2] */ 164 blo copy_loop 165 166 /* 167 * fix .rel.dyn relocations 168 */ 169 ldr r0, _TEXT_BASE /* r0 <- Text base */ 170 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 171 add r10, r10, r0 /* r10 <- sym table in FLASH */ 172 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 173 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 174 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 175 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 176fixloop: 177 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 178 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 179 ldr r1, [r2, #4] 180 and r7, r1, #0xff 181 cmp r7, #23 /* relative fixup? */ 182 beq fixrel 183 cmp r7, #2 /* absolute fixup? */ 184 beq fixabs 185 /* ignore unknown type of fixup */ 186 b fixnext 187fixabs: 188 /* absolute fix: set location to (offset) symbol value */ 189 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 190 add r1, r10, r1 /* r1 <- address of symbol in table */ 191 ldr r1, [r1, #4] /* r1 <- symbol value */ 192 add r1, r1, r9 /* r1 <- relocated sym addr */ 193 b fixnext 194fixrel: 195 /* relative fix: increase location by offset */ 196 ldr r1, [r0] 197 add r1, r1, r9 198fixnext: 199 str r1, [r0] 200 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 201 cmp r2, r3 202 blo fixloop 203 204relocate_done: 205 206 mov pc, lr 207 208_image_copy_end_ofs: 209 .word __image_copy_end - _start 210_rel_dyn_start_ofs: 211 .word __rel_dyn_start - _start 212_rel_dyn_end_ofs: 213 .word __rel_dyn_end - _start 214_dynsym_start_ofs: 215 .word __dynsym_start - _start 216 217#endif 218 219 .globl c_runtime_cpu_setup 220c_runtime_cpu_setup: 221 222 mov pc, lr 223 224/* 225 ************************************************************************* 226 * 227 * CPU_init_critical registers 228 * 229 * setup important registers 230 * setup memory timing 231 * 232 ************************************************************************* 233 */ 234 235 236/* Interrupt-Controller base address */ 237IC_BASE: .word 0x90050000 238#define ICMR 0x04 239 240 241/* Reset-Controller */ 242RST_BASE: .word 0x90030000 243#define RSRR 0x00 244#define RCSR 0x04 245 246 247/* PWR */ 248PWR_BASE: .word 0x90020000 249#define PSPR 0x08 250#define PPCR 0x14 251cpuspeed: .word CONFIG_SYS_CPUSPEED 252 253 254cpu_init_crit: 255 /* 256 * mask all IRQs 257 */ 258 ldr r0, IC_BASE 259 mov r1, #0x00 260 str r1, [r0, #ICMR] 261 262 /* set clock speed */ 263 ldr r0, PWR_BASE 264 ldr r1, cpuspeed 265 str r1, [r0, #PPCR] 266 267 /* 268 * before relocating, we have to setup RAM timing 269 * because memory timing is board-dependend, you will 270 * find a lowlevel_init.S in your board directory. 271 */ 272 mov ip, lr 273 bl lowlevel_init 274 mov lr, ip 275 276 /* 277 * disable MMU stuff and enable I-cache 278 */ 279 mrc p15,0,r0,c1,c0 280 bic r0, r0, #0x00002000 @ clear bit 13 (X) 281 bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM) 282 orr r0, r0, #0x00001000 @ set bit 12 (I) Icache 283 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 284 mcr p15,0,r0,c1,c0 285 286 /* 287 * flush v4 I/D caches 288 */ 289 mov r0, #0 290 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 291 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 292 293 mov pc, lr 294 295 296/* 297 ************************************************************************* 298 * 299 * Interrupt handling 300 * 301 ************************************************************************* 302 */ 303 304@ 305@ IRQ stack frame. 306@ 307#define S_FRAME_SIZE 72 308 309#define S_OLD_R0 68 310#define S_PSR 64 311#define S_PC 60 312#define S_LR 56 313#define S_SP 52 314 315#define S_IP 48 316#define S_FP 44 317#define S_R10 40 318#define S_R9 36 319#define S_R8 32 320#define S_R7 28 321#define S_R6 24 322#define S_R5 20 323#define S_R4 16 324#define S_R3 12 325#define S_R2 8 326#define S_R1 4 327#define S_R0 0 328 329#define MODE_SVC 0x13 330#define I_BIT 0x80 331 332/* 333 * use bad_save_user_regs for abort/prefetch/undef/swi ... 334 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 335 */ 336 337 .macro bad_save_user_regs 338 sub sp, sp, #S_FRAME_SIZE 339 stmia sp, {r0 - r12} @ Calling r0-r12 340 add r8, sp, #S_PC 341 342 ldr r2, IRQ_STACK_START_IN 343 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 344 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC 345 346 add r5, sp, #S_SP 347 mov r1, lr 348 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r 349 mov r0, sp 350 .endm 351 352 .macro irq_save_user_regs 353 sub sp, sp, #S_FRAME_SIZE 354 stmia sp, {r0 - r12} @ Calling r0-r12 355 add r8, sp, #S_PC 356 stmdb r8, {sp, lr}^ @ Calling SP, LR 357 str lr, [r8, #0] @ Save calling PC 358 mrs r6, spsr 359 str r6, [r8, #4] @ Save CPSR 360 str r0, [r8, #8] @ Save OLD_R0 361 mov r0, sp 362 .endm 363 364 .macro irq_restore_user_regs 365 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 366 mov r0, r0 367 ldr lr, [sp, #S_PC] @ Get PC 368 add sp, sp, #S_FRAME_SIZE 369 subs pc, lr, #4 @ return & move spsr_svc into cpsr 370 .endm 371 372 .macro get_bad_stack 373 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 374 375 str lr, [r13] @ save caller lr / spsr 376 mrs lr, spsr 377 str lr, [r13, #4] 378 379 mov r13, #MODE_SVC @ prepare SVC-Mode 380 msr spsr_c, r13 381 mov lr, pc 382 movs pc, lr 383 .endm 384 385 .macro get_irq_stack @ setup IRQ stack 386 ldr sp, IRQ_STACK_START 387 .endm 388 389 .macro get_fiq_stack @ setup FIQ stack 390 ldr sp, FIQ_STACK_START 391 .endm 392 393/* 394 * exception handlers 395 */ 396 .align 5 397undefined_instruction: 398 get_bad_stack 399 bad_save_user_regs 400 bl do_undefined_instruction 401 402 .align 5 403software_interrupt: 404 get_bad_stack 405 bad_save_user_regs 406 bl do_software_interrupt 407 408 .align 5 409prefetch_abort: 410 get_bad_stack 411 bad_save_user_regs 412 bl do_prefetch_abort 413 414 .align 5 415data_abort: 416 get_bad_stack 417 bad_save_user_regs 418 bl do_data_abort 419 420 .align 5 421not_used: 422 get_bad_stack 423 bad_save_user_regs 424 bl do_not_used 425 426#ifdef CONFIG_USE_IRQ 427 428 .align 5 429irq: 430 get_irq_stack 431 irq_save_user_regs 432 bl do_irq 433 irq_restore_user_regs 434 435 .align 5 436fiq: 437 get_fiq_stack 438 /* someone ought to write a more effiction fiq_save_user_regs */ 439 irq_save_user_regs 440 bl do_fiq 441 irq_restore_user_regs 442 443#else 444 445 .align 5 446irq: 447 get_bad_stack 448 bad_save_user_regs 449 bl do_irq 450 451 .align 5 452fiq: 453 get_bad_stack 454 bad_save_user_regs 455 bl do_fiq 456 457#endif 458 459 .align 5 460.globl reset_cpu 461reset_cpu: 462 ldr r0, RST_BASE 463 mov r1, #0x0 @ set bit 3-0 ... 464 str r1, [r0, #RCSR] @ ... to clear in RCSR 465 mov r1, #0x1 466 str r1, [r0, #RSRR] @ and perform reset 467 b reset_cpu @ silly, but repeat endlessly 468