1/* 2 * armboot - Startup Code for SA1100 CPU 3 * 4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> 7 * Copyright (c) 2001 Alex Züpke <azu@sysgo.de> 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28#include <asm-offsets.h> 29#include <config.h> 30#include <version.h> 31 32/* 33 ************************************************************************* 34 * 35 * Jump vector table as in table 3.1 in [1] 36 * 37 ************************************************************************* 38 */ 39 40 41.globl _start 42_start: b reset 43 ldr pc, _undefined_instruction 44 ldr pc, _software_interrupt 45 ldr pc, _prefetch_abort 46 ldr pc, _data_abort 47 ldr pc, _not_used 48 ldr pc, _irq 49 ldr pc, _fiq 50 51_undefined_instruction: .word undefined_instruction 52_software_interrupt: .word software_interrupt 53_prefetch_abort: .word prefetch_abort 54_data_abort: .word data_abort 55_not_used: .word not_used 56_irq: .word irq 57_fiq: .word fiq 58 59 .balignl 16,0xdeadbeef 60 61 62/* 63 ************************************************************************* 64 * 65 * Startup Code (reset vector) 66 * 67 * do important init only if we don't start from memory! 68 * relocate armboot to ram 69 * setup stack 70 * jump to second stage 71 * 72 ************************************************************************* 73 */ 74 75.globl _TEXT_BASE 76_TEXT_BASE: 77#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) 78 .word CONFIG_SPL_TEXT_BASE 79#else 80 .word CONFIG_SYS_TEXT_BASE 81#endif 82 83/* 84 * These are defined in the board-specific linker script. 85 * Subtracting _start from them lets the linker put their 86 * relative position in the executable instead of leaving 87 * them null. 88 */ 89.globl _bss_start_ofs 90_bss_start_ofs: 91 .word __bss_start - _start 92 93.globl _bss_end_ofs 94_bss_end_ofs: 95 .word __bss_end - _start 96 97.globl _end_ofs 98_end_ofs: 99 .word _end - _start 100 101#ifdef CONFIG_USE_IRQ 102/* IRQ stack memory (calculated at run-time) */ 103.globl IRQ_STACK_START 104IRQ_STACK_START: 105 .word 0x0badc0de 106 107/* IRQ stack memory (calculated at run-time) */ 108.globl FIQ_STACK_START 109FIQ_STACK_START: 110 .word 0x0badc0de 111#endif 112 113/* IRQ stack memory (calculated at run-time) + 8 bytes */ 114.globl IRQ_STACK_START_IN 115IRQ_STACK_START_IN: 116 .word 0x0badc0de 117 118/* 119 * the actual reset code 120 */ 121 122reset: 123 /* 124 * set the cpu to SVC32 mode 125 */ 126 mrs r0,cpsr 127 bic r0,r0,#0x1f 128 orr r0,r0,#0xd3 129 msr cpsr,r0 130 131 /* 132 * we do sys-critical inits only at reboot, 133 * not when booting from ram! 134 */ 135#ifndef CONFIG_SKIP_LOWLEVEL_INIT 136 bl cpu_init_crit 137#endif 138 139 bl _main 140 141/*------------------------------------------------------------------------------*/ 142 143/* 144 * void relocate_code (addr_sp, gd, addr_moni) 145 * 146 * This function relocates the monitor code. 147 */ 148 .globl relocate_code 149relocate_code: 150 mov r4, r0 /* save addr_sp */ 151 mov r5, r1 /* save addr of gd */ 152 mov r6, r2 /* save addr of destination */ 153 154 adr r0, _start 155 subs r9, r6, r0 /* r9 <- relocation offset */ 156 beq relocate_done /* skip relocation */ 157 mov r1, r6 /* r1 <- scratch for copy_loop */ 158 ldr r3, _bss_start_ofs 159 add r2, r0, r3 /* r2 <- source end address */ 160 161copy_loop: 162 ldmia r0!, {r10-r11} /* copy from source address [r0] */ 163 stmia r1!, {r10-r11} /* copy to target address [r1] */ 164 cmp r0, r2 /* until source end address [r2] */ 165 blo copy_loop 166 167#ifndef CONFIG_SPL_BUILD 168 /* 169 * fix .rel.dyn relocations 170 */ 171 ldr r0, _TEXT_BASE /* r0 <- Text base */ 172 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 173 add r10, r10, r0 /* r10 <- sym table in FLASH */ 174 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 175 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 176 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 177 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 178fixloop: 179 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 180 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 181 ldr r1, [r2, #4] 182 and r7, r1, #0xff 183 cmp r7, #23 /* relative fixup? */ 184 beq fixrel 185 cmp r7, #2 /* absolute fixup? */ 186 beq fixabs 187 /* ignore unknown type of fixup */ 188 b fixnext 189fixabs: 190 /* absolute fix: set location to (offset) symbol value */ 191 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 192 add r1, r10, r1 /* r1 <- address of symbol in table */ 193 ldr r1, [r1, #4] /* r1 <- symbol value */ 194 add r1, r1, r9 /* r1 <- relocated sym addr */ 195 b fixnext 196fixrel: 197 /* relative fix: increase location by offset */ 198 ldr r1, [r0] 199 add r1, r1, r9 200fixnext: 201 str r1, [r0] 202 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 203 cmp r2, r3 204 blo fixloop 205#endif 206 207relocate_done: 208 209 mov pc, lr 210 211_rel_dyn_start_ofs: 212 .word __rel_dyn_start - _start 213_rel_dyn_end_ofs: 214 .word __rel_dyn_end - _start 215_dynsym_start_ofs: 216 .word __dynsym_start - _start 217 218 .globl c_runtime_cpu_setup 219c_runtime_cpu_setup: 220 221 mov pc, lr 222 223/* 224 ************************************************************************* 225 * 226 * CPU_init_critical registers 227 * 228 * setup important registers 229 * setup memory timing 230 * 231 ************************************************************************* 232 */ 233 234 235/* Interrupt-Controller base address */ 236IC_BASE: .word 0x90050000 237#define ICMR 0x04 238 239 240/* Reset-Controller */ 241RST_BASE: .word 0x90030000 242#define RSRR 0x00 243#define RCSR 0x04 244 245 246/* PWR */ 247PWR_BASE: .word 0x90020000 248#define PSPR 0x08 249#define PPCR 0x14 250cpuspeed: .word CONFIG_SYS_CPUSPEED 251 252 253cpu_init_crit: 254 /* 255 * mask all IRQs 256 */ 257 ldr r0, IC_BASE 258 mov r1, #0x00 259 str r1, [r0, #ICMR] 260 261 /* set clock speed */ 262 ldr r0, PWR_BASE 263 ldr r1, cpuspeed 264 str r1, [r0, #PPCR] 265 266 /* 267 * before relocating, we have to setup RAM timing 268 * because memory timing is board-dependend, you will 269 * find a lowlevel_init.S in your board directory. 270 */ 271 mov ip, lr 272 bl lowlevel_init 273 mov lr, ip 274 275 /* 276 * disable MMU stuff and enable I-cache 277 */ 278 mrc p15,0,r0,c1,c0 279 bic r0, r0, #0x00002000 @ clear bit 13 (X) 280 bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM) 281 orr r0, r0, #0x00001000 @ set bit 12 (I) Icache 282 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 283 mcr p15,0,r0,c1,c0 284 285 /* 286 * flush v4 I/D caches 287 */ 288 mov r0, #0 289 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 290 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 291 292 mov pc, lr 293 294 295/* 296 ************************************************************************* 297 * 298 * Interrupt handling 299 * 300 ************************************************************************* 301 */ 302 303@ 304@ IRQ stack frame. 305@ 306#define S_FRAME_SIZE 72 307 308#define S_OLD_R0 68 309#define S_PSR 64 310#define S_PC 60 311#define S_LR 56 312#define S_SP 52 313 314#define S_IP 48 315#define S_FP 44 316#define S_R10 40 317#define S_R9 36 318#define S_R8 32 319#define S_R7 28 320#define S_R6 24 321#define S_R5 20 322#define S_R4 16 323#define S_R3 12 324#define S_R2 8 325#define S_R1 4 326#define S_R0 0 327 328#define MODE_SVC 0x13 329#define I_BIT 0x80 330 331/* 332 * use bad_save_user_regs for abort/prefetch/undef/swi ... 333 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 334 */ 335 336 .macro bad_save_user_regs 337 sub sp, sp, #S_FRAME_SIZE 338 stmia sp, {r0 - r12} @ Calling r0-r12 339 add r8, sp, #S_PC 340 341 ldr r2, IRQ_STACK_START_IN 342 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 343 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC 344 345 add r5, sp, #S_SP 346 mov r1, lr 347 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r 348 mov r0, sp 349 .endm 350 351 .macro irq_save_user_regs 352 sub sp, sp, #S_FRAME_SIZE 353 stmia sp, {r0 - r12} @ Calling r0-r12 354 add r8, sp, #S_PC 355 stmdb r8, {sp, lr}^ @ Calling SP, LR 356 str lr, [r8, #0] @ Save calling PC 357 mrs r6, spsr 358 str r6, [r8, #4] @ Save CPSR 359 str r0, [r8, #8] @ Save OLD_R0 360 mov r0, sp 361 .endm 362 363 .macro irq_restore_user_regs 364 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 365 mov r0, r0 366 ldr lr, [sp, #S_PC] @ Get PC 367 add sp, sp, #S_FRAME_SIZE 368 subs pc, lr, #4 @ return & move spsr_svc into cpsr 369 .endm 370 371 .macro get_bad_stack 372 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 373 374 str lr, [r13] @ save caller lr / spsr 375 mrs lr, spsr 376 str lr, [r13, #4] 377 378 mov r13, #MODE_SVC @ prepare SVC-Mode 379 msr spsr_c, r13 380 mov lr, pc 381 movs pc, lr 382 .endm 383 384 .macro get_irq_stack @ setup IRQ stack 385 ldr sp, IRQ_STACK_START 386 .endm 387 388 .macro get_fiq_stack @ setup FIQ stack 389 ldr sp, FIQ_STACK_START 390 .endm 391 392/* 393 * exception handlers 394 */ 395 .align 5 396undefined_instruction: 397 get_bad_stack 398 bad_save_user_regs 399 bl do_undefined_instruction 400 401 .align 5 402software_interrupt: 403 get_bad_stack 404 bad_save_user_regs 405 bl do_software_interrupt 406 407 .align 5 408prefetch_abort: 409 get_bad_stack 410 bad_save_user_regs 411 bl do_prefetch_abort 412 413 .align 5 414data_abort: 415 get_bad_stack 416 bad_save_user_regs 417 bl do_data_abort 418 419 .align 5 420not_used: 421 get_bad_stack 422 bad_save_user_regs 423 bl do_not_used 424 425#ifdef CONFIG_USE_IRQ 426 427 .align 5 428irq: 429 get_irq_stack 430 irq_save_user_regs 431 bl do_irq 432 irq_restore_user_regs 433 434 .align 5 435fiq: 436 get_fiq_stack 437 /* someone ought to write a more effiction fiq_save_user_regs */ 438 irq_save_user_regs 439 bl do_fiq 440 irq_restore_user_regs 441 442#else 443 444 .align 5 445irq: 446 get_bad_stack 447 bad_save_user_regs 448 bl do_irq 449 450 .align 5 451fiq: 452 get_bad_stack 453 bad_save_user_regs 454 bl do_fiq 455 456#endif 457 458 .align 5 459.globl reset_cpu 460reset_cpu: 461 ldr r0, RST_BASE 462 mov r1, #0x0 @ set bit 3-0 ... 463 str r1, [r0, #RCSR] @ ... to clear in RCSR 464 mov r1, #0x1 465 str r1, [r0, #RSRR] @ and perform reset 466 b reset_cpu @ silly, but repeat endlessly 467