184ad6884SPeter Tyser /* 284ad6884SPeter Tyser * (C) Copyright 2002 384ad6884SPeter Tyser * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 484ad6884SPeter Tyser * Marius Groeger <mgroeger@sysgo.de> 584ad6884SPeter Tyser * 684ad6884SPeter Tyser * (C) Copyright 2002 784ad6884SPeter Tyser * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 884ad6884SPeter Tyser * Alex Zuepke <azu@sysgo.de> 984ad6884SPeter Tyser * 101a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 1184ad6884SPeter Tyser */ 1284ad6884SPeter Tyser 1384ad6884SPeter Tyser /* 1484ad6884SPeter Tyser * CPU specific code 1584ad6884SPeter Tyser */ 1684ad6884SPeter Tyser 1784ad6884SPeter Tyser #include <common.h> 1884ad6884SPeter Tyser #include <command.h> 1984ad6884SPeter Tyser #include <asm/system.h> 20*cd6cc344SAlbert ARIBAUD #include <asm/io.h> 2184ad6884SPeter Tyser 2284ad6884SPeter Tyser static void cache_flush(void); 2384ad6884SPeter Tyser cleanup_before_linux(void)2484ad6884SPeter Tyserint cleanup_before_linux (void) 2584ad6884SPeter Tyser { 2684ad6884SPeter Tyser /* 2784ad6884SPeter Tyser * this function is called just before we call linux 2884ad6884SPeter Tyser * it prepares the processor for linux 2984ad6884SPeter Tyser * 3084ad6884SPeter Tyser * just disable everything that can disturb booting linux 3184ad6884SPeter Tyser */ 3284ad6884SPeter Tyser 3384ad6884SPeter Tyser disable_interrupts (); 3484ad6884SPeter Tyser 3584ad6884SPeter Tyser /* turn off I-cache */ 3684ad6884SPeter Tyser icache_disable(); 3784ad6884SPeter Tyser dcache_disable(); 3884ad6884SPeter Tyser 3984ad6884SPeter Tyser /* flush I-cache */ 4084ad6884SPeter Tyser cache_flush(); 4184ad6884SPeter Tyser 4284ad6884SPeter Tyser return (0); 4384ad6884SPeter Tyser } 4484ad6884SPeter Tyser 4584ad6884SPeter Tyser /* flush I/D-cache */ cache_flush(void)4684ad6884SPeter Tyserstatic void cache_flush (void) 4784ad6884SPeter Tyser { 4884ad6884SPeter Tyser unsigned long i = 0; 4984ad6884SPeter Tyser 5084ad6884SPeter Tyser asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); 5184ad6884SPeter Tyser } 52*cd6cc344SAlbert ARIBAUD 53*cd6cc344SAlbert ARIBAUD #define RST_BASE 0x90030000 54*cd6cc344SAlbert ARIBAUD #define RSRR 0x00 55*cd6cc344SAlbert ARIBAUD #define RCSR 0x04 56*cd6cc344SAlbert ARIBAUD reset_cpu(ulong addr)57*cd6cc344SAlbert ARIBAUD__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused))) 58*cd6cc344SAlbert ARIBAUD { 59*cd6cc344SAlbert ARIBAUD /* repeat endlessly */ 60*cd6cc344SAlbert ARIBAUD while (1) { 61*cd6cc344SAlbert ARIBAUD writel(0, RST_BASE + RCSR); 62*cd6cc344SAlbert ARIBAUD writel(1, RST_BASE + RSRR); 63*cd6cc344SAlbert ARIBAUD } 64*cd6cc344SAlbert ARIBAUD } 65