1/* 2 * armboot - Startup Code for XScale CPU-core 3 * 4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> 7 * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de> 8 * Copyright (C) 2001 Marius Groger <mag@sysgo.de> 9 * Copyright (C) 2002 Alex Zupke <azu@sysgo.de> 10 * Copyright (C) 2002 Gary Jennejohn <garyj@denx.de> 11 * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net> 12 * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de> 13 * Copyright (C) 2003 Kshitij <kshitij@ti.com> 14 * Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com> 15 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> 16 * Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com> 17 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> 18 * 19 * See file CREDITS for list of people who contributed to this 20 * project. 21 * 22 * This program is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU General Public License as 24 * published by the Free Software Foundation; either version 2 of 25 * the License, or (at your option) any later version. 26 * 27 * This program is distributed in the hope that it will be useful, 28 * but WITHOUT ANY WARRANTY; without even the implied warranty of 29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 30 * GNU General Public License for more details. 31 * 32 * You should have received a copy of the GNU General Public License 33 * along with this program; if not, write to the Free Software 34 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 35 * MA 02111-1307 USA 36 */ 37 38#include <asm-offsets.h> 39#include <config.h> 40#include <version.h> 41 42#ifdef CONFIG_CPU_PXA25X 43#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800) 44#error "Init SP address must be set to 0xfffff800 for PXA250" 45#endif 46#endif 47 48.globl _start 49_start: b reset 50#ifdef CONFIG_SPL_BUILD 51 ldr pc, _hang 52 ldr pc, _hang 53 ldr pc, _hang 54 ldr pc, _hang 55 ldr pc, _hang 56 ldr pc, _hang 57 ldr pc, _hang 58 59_hang: 60 .word do_hang 61 .word 0x12345678 62 .word 0x12345678 63 .word 0x12345678 64 .word 0x12345678 65 .word 0x12345678 66 .word 0x12345678 67 .word 0x12345678 /* now 16*4=64 */ 68#else 69 ldr pc, _undefined_instruction 70 ldr pc, _software_interrupt 71 ldr pc, _prefetch_abort 72 ldr pc, _data_abort 73 ldr pc, _not_used 74 ldr pc, _irq 75 ldr pc, _fiq 76 77_undefined_instruction: .word undefined_instruction 78_software_interrupt: .word software_interrupt 79_prefetch_abort: .word prefetch_abort 80_data_abort: .word data_abort 81_not_used: .word not_used 82_irq: .word irq 83_fiq: .word fiq 84_pad: .word 0x12345678 /* now 16*4=64 */ 85#endif /* CONFIG_SPL_BUILD */ 86.global _end_vect 87_end_vect: 88 89 .balignl 16,0xdeadbeef 90/* 91 ************************************************************************* 92 * 93 * Startup Code (reset vector) 94 * 95 * do important init only if we don't start from memory! 96 * setup Memory and board specific bits prior to relocation. 97 * relocate armboot to ram 98 * setup stack 99 * 100 ************************************************************************* 101 */ 102 103.globl _TEXT_BASE 104_TEXT_BASE: 105#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) 106 .word CONFIG_SPL_TEXT_BASE 107#else 108 .word CONFIG_SYS_TEXT_BASE 109#endif 110 111/* 112 * These are defined in the board-specific linker script. 113 * Subtracting _start from them lets the linker put their 114 * relative position in the executable instead of leaving 115 * them null. 116 */ 117.globl _bss_start_ofs 118_bss_start_ofs: 119 .word __bss_start - _start 120 121.globl _bss_end_ofs 122_bss_end_ofs: 123 .word __bss_end - _start 124 125.globl _end_ofs 126_end_ofs: 127 .word _end - _start 128 129#ifdef CONFIG_USE_IRQ 130/* IRQ stack memory (calculated at run-time) */ 131.globl IRQ_STACK_START 132IRQ_STACK_START: 133 .word 0x0badc0de 134 135/* IRQ stack memory (calculated at run-time) */ 136.globl FIQ_STACK_START 137FIQ_STACK_START: 138 .word 0x0badc0de 139#endif 140 141/* IRQ stack memory (calculated at run-time) + 8 bytes */ 142.globl IRQ_STACK_START_IN 143IRQ_STACK_START_IN: 144 .word 0x0badc0de 145 146/* 147 * the actual reset code 148 */ 149 150reset: 151 /* 152 * set the cpu to SVC32 mode 153 */ 154 mrs r0,cpsr 155 bic r0,r0,#0x1f 156 orr r0,r0,#0xd3 157 msr cpsr,r0 158 159#ifndef CONFIG_SKIP_LOWLEVEL_INIT 160 bl cpu_init_crit 161#endif 162 163#ifdef CONFIG_CPU_PXA25X 164 bl lock_cache_for_stack 165#endif 166 167 bl _main 168 169/*------------------------------------------------------------------------------*/ 170#ifndef CONFIG_SPL_BUILD 171/* 172 * void relocate_code(addr_moni) 173 * 174 * This function relocates the monitor code. 175 */ 176 .globl relocate_code 177relocate_code: 178 mov r6, r0 /* save addr of destination */ 179 180/* Disable the Dcache RAM lock for stack now */ 181#ifdef CONFIG_CPU_PXA25X 182 mov r12, lr 183 bl cpu_init_crit 184 mov lr, r12 185#endif 186 187 adr r0, _start 188 subs r9, r6, r0 /* r9 <- relocation offset */ 189 beq relocate_done /* skip relocation */ 190 mov r1, r6 /* r1 <- scratch for copy_loop */ 191 ldr r3, _image_copy_end_ofs 192 add r2, r0, r3 /* r2 <- source end address */ 193 194copy_loop: 195 ldmia r0!, {r10-r11} /* copy from source address [r0] */ 196 stmia r1!, {r10-r11} /* copy to target address [r1] */ 197 cmp r0, r2 /* until source end address [r2] */ 198 blo copy_loop 199 200 /* 201 * fix .rel.dyn relocations 202 */ 203 ldr r0, _TEXT_BASE /* r0 <- Text base */ 204 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 205 add r10, r10, r0 /* r10 <- sym table in FLASH */ 206 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 207 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 208 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 209 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 210fixloop: 211 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 212 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 213 ldr r1, [r2, #4] 214 and r7, r1, #0xff 215 cmp r7, #23 /* relative fixup? */ 216 beq fixrel 217 cmp r7, #2 /* absolute fixup? */ 218 beq fixabs 219 /* ignore unknown type of fixup */ 220 b fixnext 221fixabs: 222 /* absolute fix: set location to (offset) symbol value */ 223 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 224 add r1, r10, r1 /* r1 <- address of symbol in table */ 225 ldr r1, [r1, #4] /* r1 <- symbol value */ 226 add r1, r1, r9 /* r1 <- relocated sym addr */ 227 b fixnext 228fixrel: 229 /* relative fix: increase location by offset */ 230 ldr r1, [r0] 231 add r1, r1, r9 232fixnext: 233 str r1, [r0] 234 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 235 cmp r2, r3 236 blo fixloop 237 238relocate_done: 239 240 bx lr 241 242_image_copy_end_ofs: 243 .word __image_copy_end - _start 244_rel_dyn_start_ofs: 245 .word __rel_dyn_start - _start 246_rel_dyn_end_ofs: 247 .word __rel_dyn_end - _start 248_dynsym_start_ofs: 249 .word __dynsym_start - _start 250 251#endif 252 253 .globl c_runtime_cpu_setup 254c_runtime_cpu_setup: 255 256 bx lr 257 258/* 259 ************************************************************************* 260 * 261 * CPU_init_critical registers 262 * 263 * setup important registers 264 * setup memory timing 265 * 266 ************************************************************************* 267 */ 268#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X) 269cpu_init_crit: 270 /* 271 * flush v4 I/D caches 272 */ 273 mov r0, #0 274 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 275 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 276 277 /* 278 * disable MMU stuff and caches 279 */ 280 mrc p15, 0, r0, c1, c0, 0 281 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 282 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 283 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 284 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 285 mcr p15, 0, r0, c1, c0, 0 286 287 mov pc, lr /* back to my caller */ 288#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */ 289 290#ifndef CONFIG_SPL_BUILD 291/* 292 ************************************************************************* 293 * 294 * Interrupt handling 295 * 296 ************************************************************************* 297 */ 298@ 299@ IRQ stack frame. 300@ 301#define S_FRAME_SIZE 72 302 303#define S_OLD_R0 68 304#define S_PSR 64 305#define S_PC 60 306#define S_LR 56 307#define S_SP 52 308 309#define S_IP 48 310#define S_FP 44 311#define S_R10 40 312#define S_R9 36 313#define S_R8 32 314#define S_R7 28 315#define S_R6 24 316#define S_R5 20 317#define S_R4 16 318#define S_R3 12 319#define S_R2 8 320#define S_R1 4 321#define S_R0 0 322 323#define MODE_SVC 0x13 324#define I_BIT 0x80 325 326/* 327 * use bad_save_user_regs for abort/prefetch/undef/swi ... 328 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 329 */ 330 331 .macro bad_save_user_regs 332 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack 333 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 334 335 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack 336 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) 337 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 338 339 add r5, sp, #S_SP 340 mov r1, lr 341 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 342 mov r0, sp @ save current stack into r0 (param register) 343 .endm 344 345 .macro irq_save_user_regs 346 sub sp, sp, #S_FRAME_SIZE 347 stmia sp, {r0 - r12} @ Calling r0-r12 348 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 349 stmdb r8, {sp, lr}^ @ Calling SP, LR 350 str lr, [r8, #0] @ Save calling PC 351 mrs r6, spsr 352 str r6, [r8, #4] @ Save CPSR 353 str r0, [r8, #8] @ Save OLD_R0 354 mov r0, sp 355 .endm 356 357 .macro irq_restore_user_regs 358 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 359 mov r0, r0 360 ldr lr, [sp, #S_PC] @ Get PC 361 add sp, sp, #S_FRAME_SIZE 362 subs pc, lr, #4 @ return & move spsr_svc into cpsr 363 .endm 364 365 .macro get_bad_stack 366 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) 367 368 str lr, [r13] @ save caller lr in position 0 of saved stack 369 mrs lr, spsr @ get the spsr 370 str lr, [r13, #4] @ save spsr in position 1 of saved stack 371 372 mov r13, #MODE_SVC @ prepare SVC-Mode 373 @ msr spsr_c, r13 374 msr spsr, r13 @ switch modes, make sure moves will execute 375 mov lr, pc @ capture return pc 376 movs pc, lr @ jump to next instruction & switch modes. 377 .endm 378 379 .macro get_bad_stack_swi 380 sub r13, r13, #4 @ space on current stack for scratch reg. 381 str r0, [r13] @ save R0's value. 382 ldr r0, IRQ_STACK_START_IN @ get data regions start 383 str lr, [r0] @ save caller lr in position 0 of saved stack 384 mrs lr, spsr @ get the spsr 385 str lr, [r0, #4] @ save spsr in position 1 of saved stack 386 ldr lr, [r0] @ restore lr 387 ldr r0, [r13] @ restore r0 388 add r13, r13, #4 @ pop stack entry 389 .endm 390 391 .macro get_irq_stack @ setup IRQ stack 392 ldr sp, IRQ_STACK_START 393 .endm 394 395 .macro get_fiq_stack @ setup FIQ stack 396 ldr sp, FIQ_STACK_START 397 .endm 398#endif /* CONFIG_SPL_BUILD */ 399 400/* 401 * exception handlers 402 */ 403#ifdef CONFIG_SPL_BUILD 404 .align 5 405do_hang: 406 ldr sp, _TEXT_BASE /* use 32 words about stack */ 407 bl hang /* hang and never return */ 408#else /* !CONFIG_SPL_BUILD */ 409 .align 5 410undefined_instruction: 411 get_bad_stack 412 bad_save_user_regs 413 bl do_undefined_instruction 414 415 .align 5 416software_interrupt: 417 get_bad_stack_swi 418 bad_save_user_regs 419 bl do_software_interrupt 420 421 .align 5 422prefetch_abort: 423 get_bad_stack 424 bad_save_user_regs 425 bl do_prefetch_abort 426 427 .align 5 428data_abort: 429 get_bad_stack 430 bad_save_user_regs 431 bl do_data_abort 432 433 .align 5 434not_used: 435 get_bad_stack 436 bad_save_user_regs 437 bl do_not_used 438 439#ifdef CONFIG_USE_IRQ 440 441 .align 5 442irq: 443 get_irq_stack 444 irq_save_user_regs 445 bl do_irq 446 irq_restore_user_regs 447 448 .align 5 449fiq: 450 get_fiq_stack 451 /* someone ought to write a more effiction fiq_save_user_regs */ 452 irq_save_user_regs 453 bl do_fiq 454 irq_restore_user_regs 455 456#else 457 458 .align 5 459irq: 460 get_bad_stack 461 bad_save_user_regs 462 bl do_irq 463 464 .align 5 465fiq: 466 get_bad_stack 467 bad_save_user_regs 468 bl do_fiq 469 470#endif 471 .align 5 472#endif /* CONFIG_SPL_BUILD */ 473 474 475/* 476 * Enable MMU to use DCache as DRAM. 477 * 478 * This is useful on PXA25x and PXA26x in early bootstages, where there is no 479 * other possible memory available to hold stack. 480 */ 481#ifdef CONFIG_CPU_PXA25X 482.macro CPWAIT reg 483 mrc p15, 0, \reg, c2, c0, 0 484 mov \reg, \reg 485 sub pc, pc, #4 486.endm 487lock_cache_for_stack: 488 /* Domain access -- enable for all CPs */ 489 ldr r0, =0x0000ffff 490 mcr p15, 0, r0, c3, c0, 0 491 492 /* Point TTBR to MMU table */ 493 ldr r0, =mmutable 494 mcr p15, 0, r0, c2, c0, 0 495 496 /* Kick in MMU, ICache, DCache, BTB */ 497 mrc p15, 0, r0, c1, c0, 0 498 bic r0, #0x1b00 499 bic r0, #0x0087 500 orr r0, #0x1800 501 orr r0, #0x0005 502 mcr p15, 0, r0, c1, c0, 0 503 CPWAIT r0 504 505 /* Unlock Icache, Dcache */ 506 mcr p15, 0, r0, c9, c1, 1 507 mcr p15, 0, r0, c9, c2, 1 508 509 /* Flush Icache, Dcache, BTB */ 510 mcr p15, 0, r0, c7, c7, 0 511 512 /* Unlock I-TLB, D-TLB */ 513 mcr p15, 0, r0, c10, c4, 1 514 mcr p15, 0, r0, c10, c8, 1 515 516 /* Flush TLB */ 517 mcr p15, 0, r0, c8, c7, 0 518 519 /* Allocate 4096 bytes of Dcache as RAM */ 520 521 /* Drain pending loads and stores */ 522 mcr p15, 0, r0, c7, c10, 4 523 524 mov r4, #0x00 525 mov r5, #0x00 526 mov r2, #0x01 527 mcr p15, 0, r0, c9, c2, 0 528 CPWAIT r0 529 530 /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */ 531 mov r0, #128 532 ldr r1, =0xfffff000 533 534alloc: 535 mcr p15, 0, r1, c7, c2, 5 536 /* Drain pending loads and stores */ 537 mcr p15, 0, r0, c7, c10, 4 538 strd r4, [r1], #8 539 strd r4, [r1], #8 540 strd r4, [r1], #8 541 strd r4, [r1], #8 542 subs r0, #0x01 543 bne alloc 544 /* Drain pending loads and stores */ 545 mcr p15, 0, r0, c7, c10, 4 546 mov r2, #0x00 547 mcr p15, 0, r2, c9, c2, 0 548 CPWAIT r0 549 550 mov pc, lr 551 552.section .mmutable, "a" 553mmutable: 554 .align 14 555 /* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */ 556 .set __base, 0 557 .rept 0xfff 558 .word (__base << 20) | 0xc12 559 .set __base, __base + 1 560 .endr 561 562 /* 0xfff00000 : 1:1, cached mapping */ 563 .word (0xfff << 20) | 0x1c1e 564#endif /* CONFIG_CPU_PXA25X */ 565