1/* 2 * armboot - Startup Code for XScale CPU-core 3 * 4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> 7 * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de> 8 * Copyright (C) 2001 Marius Groger <mag@sysgo.de> 9 * Copyright (C) 2002 Alex Zupke <azu@sysgo.de> 10 * Copyright (C) 2002 Gary Jennejohn <garyj@denx.de> 11 * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net> 12 * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de> 13 * Copyright (C) 2003 Kshitij <kshitij@ti.com> 14 * Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com> 15 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> 16 * Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com> 17 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> 18 * 19 * See file CREDITS for list of people who contributed to this 20 * project. 21 * 22 * This program is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU General Public License as 24 * published by the Free Software Foundation; either version 2 of 25 * the License, or (at your option) any later version. 26 * 27 * This program is distributed in the hope that it will be useful, 28 * but WITHOUT ANY WARRANTY; without even the implied warranty of 29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 30 * GNU General Public License for more details. 31 * 32 * You should have received a copy of the GNU General Public License 33 * along with this program; if not, write to the Free Software 34 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 35 * MA 02111-1307 USA 36 */ 37 38#include <asm-offsets.h> 39#include <config.h> 40#include <version.h> 41 42#ifdef CONFIG_CPU_PXA25X 43#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800) 44#error "Init SP address must be set to 0xfffff800 for PXA250" 45#endif 46#endif 47 48.globl _start 49_start: b reset 50#ifdef CONFIG_SPL_BUILD 51 ldr pc, _hang 52 ldr pc, _hang 53 ldr pc, _hang 54 ldr pc, _hang 55 ldr pc, _hang 56 ldr pc, _hang 57 ldr pc, _hang 58 59_hang: 60 .word do_hang 61 .word 0x12345678 62 .word 0x12345678 63 .word 0x12345678 64 .word 0x12345678 65 .word 0x12345678 66 .word 0x12345678 67 .word 0x12345678 /* now 16*4=64 */ 68#else 69 ldr pc, _undefined_instruction 70 ldr pc, _software_interrupt 71 ldr pc, _prefetch_abort 72 ldr pc, _data_abort 73 ldr pc, _not_used 74 ldr pc, _irq 75 ldr pc, _fiq 76 77_undefined_instruction: .word undefined_instruction 78_software_interrupt: .word software_interrupt 79_prefetch_abort: .word prefetch_abort 80_data_abort: .word data_abort 81_not_used: .word not_used 82_irq: .word irq 83_fiq: .word fiq 84_pad: .word 0x12345678 /* now 16*4=64 */ 85#endif /* CONFIG_SPL_BUILD */ 86.global _end_vect 87_end_vect: 88 89 .balignl 16,0xdeadbeef 90/* 91 ************************************************************************* 92 * 93 * Startup Code (reset vector) 94 * 95 * do important init only if we don't start from memory! 96 * setup Memory and board specific bits prior to relocation. 97 * relocate armboot to ram 98 * setup stack 99 * 100 ************************************************************************* 101 */ 102 103.globl _TEXT_BASE 104_TEXT_BASE: 105#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) 106 .word CONFIG_SPL_TEXT_BASE 107#else 108 .word CONFIG_SYS_TEXT_BASE 109#endif 110 111/* 112 * These are defined in the board-specific linker script. 113 * Subtracting _start from them lets the linker put their 114 * relative position in the executable instead of leaving 115 * them null. 116 */ 117.globl _bss_start_ofs 118_bss_start_ofs: 119 .word __bss_start - _start 120 121.globl _bss_end_ofs 122_bss_end_ofs: 123 .word __bss_end - _start 124 125.globl _end_ofs 126_end_ofs: 127 .word _end - _start 128 129#ifdef CONFIG_USE_IRQ 130/* IRQ stack memory (calculated at run-time) */ 131.globl IRQ_STACK_START 132IRQ_STACK_START: 133 .word 0x0badc0de 134 135/* IRQ stack memory (calculated at run-time) */ 136.globl FIQ_STACK_START 137FIQ_STACK_START: 138 .word 0x0badc0de 139#endif 140 141/* IRQ stack memory (calculated at run-time) + 8 bytes */ 142.globl IRQ_STACK_START_IN 143IRQ_STACK_START_IN: 144 .word 0x0badc0de 145 146/* 147 * the actual reset code 148 */ 149 150reset: 151 /* 152 * set the cpu to SVC32 mode 153 */ 154 mrs r0,cpsr 155 bic r0,r0,#0x1f 156 orr r0,r0,#0xd3 157 msr cpsr,r0 158 159#ifndef CONFIG_SKIP_LOWLEVEL_INIT 160 bl cpu_init_crit 161#endif 162 163#ifdef CONFIG_CPU_PXA25X 164 bl lock_cache_for_stack 165#endif 166 167 bl _main 168 169/*------------------------------------------------------------------------------*/ 170#ifndef CONFIG_SPL_BUILD 171/* 172 * void relocate_code (addr_sp, gd, addr_moni) 173 * 174 * This function relocates the monitor code. 175 */ 176 .globl relocate_code 177relocate_code: 178 mov r4, r0 /* save addr_sp */ 179 mov r5, r1 /* save addr of gd */ 180 mov r6, r2 /* save addr of destination */ 181 182/* Disable the Dcache RAM lock for stack now */ 183#ifdef CONFIG_CPU_PXA25X 184 mov r12, lr 185 bl cpu_init_crit 186 mov lr, r12 187#endif 188 189 adr r0, _start 190 subs r9, r6, r0 /* r9 <- relocation offset */ 191 beq relocate_done /* skip relocation */ 192 mov r1, r6 /* r1 <- scratch for copy_loop */ 193 ldr r3, _bss_start_ofs 194 add r2, r0, r3 /* r2 <- source end address */ 195 196copy_loop: 197 ldmia r0!, {r10-r11} /* copy from source address [r0] */ 198 stmia r1!, {r10-r11} /* copy to target address [r1] */ 199 cmp r0, r2 /* until source end address [r2] */ 200 blo copy_loop 201 202#ifndef CONFIG_SPL_BUILD 203 /* 204 * fix .rel.dyn relocations 205 */ 206 ldr r0, _TEXT_BASE /* r0 <- Text base */ 207 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 208 add r10, r10, r0 /* r10 <- sym table in FLASH */ 209 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 210 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 211 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 212 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 213fixloop: 214 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 215 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 216 ldr r1, [r2, #4] 217 and r7, r1, #0xff 218 cmp r7, #23 /* relative fixup? */ 219 beq fixrel 220 cmp r7, #2 /* absolute fixup? */ 221 beq fixabs 222 /* ignore unknown type of fixup */ 223 b fixnext 224fixabs: 225 /* absolute fix: set location to (offset) symbol value */ 226 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 227 add r1, r10, r1 /* r1 <- address of symbol in table */ 228 ldr r1, [r1, #4] /* r1 <- symbol value */ 229 add r1, r1, r9 /* r1 <- relocated sym addr */ 230 b fixnext 231fixrel: 232 /* relative fix: increase location by offset */ 233 ldr r1, [r0] 234 add r1, r1, r9 235fixnext: 236 str r1, [r0] 237 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 238 cmp r2, r3 239 blo fixloop 240#endif 241 242relocate_done: 243 244 bx lr 245 246_rel_dyn_start_ofs: 247 .word __rel_dyn_start - _start 248_rel_dyn_end_ofs: 249 .word __rel_dyn_end - _start 250_dynsym_start_ofs: 251 .word __dynsym_start - _start 252 253#endif 254 255 .globl c_runtime_cpu_setup 256c_runtime_cpu_setup: 257 258 bx lr 259 260/* 261 ************************************************************************* 262 * 263 * CPU_init_critical registers 264 * 265 * setup important registers 266 * setup memory timing 267 * 268 ************************************************************************* 269 */ 270#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X) 271cpu_init_crit: 272 /* 273 * flush v4 I/D caches 274 */ 275 mov r0, #0 276 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 277 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 278 279 /* 280 * disable MMU stuff and caches 281 */ 282 mrc p15, 0, r0, c1, c0, 0 283 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 284 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 285 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 286 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 287 mcr p15, 0, r0, c1, c0, 0 288 289 mov pc, lr /* back to my caller */ 290#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */ 291 292#ifndef CONFIG_SPL_BUILD 293/* 294 ************************************************************************* 295 * 296 * Interrupt handling 297 * 298 ************************************************************************* 299 */ 300@ 301@ IRQ stack frame. 302@ 303#define S_FRAME_SIZE 72 304 305#define S_OLD_R0 68 306#define S_PSR 64 307#define S_PC 60 308#define S_LR 56 309#define S_SP 52 310 311#define S_IP 48 312#define S_FP 44 313#define S_R10 40 314#define S_R9 36 315#define S_R8 32 316#define S_R7 28 317#define S_R6 24 318#define S_R5 20 319#define S_R4 16 320#define S_R3 12 321#define S_R2 8 322#define S_R1 4 323#define S_R0 0 324 325#define MODE_SVC 0x13 326#define I_BIT 0x80 327 328/* 329 * use bad_save_user_regs for abort/prefetch/undef/swi ... 330 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 331 */ 332 333 .macro bad_save_user_regs 334 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack 335 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 336 337 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack 338 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) 339 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 340 341 add r5, sp, #S_SP 342 mov r1, lr 343 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 344 mov r0, sp @ save current stack into r0 (param register) 345 .endm 346 347 .macro irq_save_user_regs 348 sub sp, sp, #S_FRAME_SIZE 349 stmia sp, {r0 - r12} @ Calling r0-r12 350 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 351 stmdb r8, {sp, lr}^ @ Calling SP, LR 352 str lr, [r8, #0] @ Save calling PC 353 mrs r6, spsr 354 str r6, [r8, #4] @ Save CPSR 355 str r0, [r8, #8] @ Save OLD_R0 356 mov r0, sp 357 .endm 358 359 .macro irq_restore_user_regs 360 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 361 mov r0, r0 362 ldr lr, [sp, #S_PC] @ Get PC 363 add sp, sp, #S_FRAME_SIZE 364 subs pc, lr, #4 @ return & move spsr_svc into cpsr 365 .endm 366 367 .macro get_bad_stack 368 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) 369 370 str lr, [r13] @ save caller lr in position 0 of saved stack 371 mrs lr, spsr @ get the spsr 372 str lr, [r13, #4] @ save spsr in position 1 of saved stack 373 374 mov r13, #MODE_SVC @ prepare SVC-Mode 375 @ msr spsr_c, r13 376 msr spsr, r13 @ switch modes, make sure moves will execute 377 mov lr, pc @ capture return pc 378 movs pc, lr @ jump to next instruction & switch modes. 379 .endm 380 381 .macro get_bad_stack_swi 382 sub r13, r13, #4 @ space on current stack for scratch reg. 383 str r0, [r13] @ save R0's value. 384 ldr r0, IRQ_STACK_START_IN @ get data regions start 385 str lr, [r0] @ save caller lr in position 0 of saved stack 386 mrs r0, spsr @ get the spsr 387 str lr, [r0, #4] @ save spsr in position 1 of saved stack 388 ldr r0, [r13] @ restore r0 389 add r13, r13, #4 @ pop stack entry 390 .endm 391 392 .macro get_irq_stack @ setup IRQ stack 393 ldr sp, IRQ_STACK_START 394 .endm 395 396 .macro get_fiq_stack @ setup FIQ stack 397 ldr sp, FIQ_STACK_START 398 .endm 399#endif /* CONFIG_SPL_BUILD */ 400 401/* 402 * exception handlers 403 */ 404#ifdef CONFIG_SPL_BUILD 405 .align 5 406do_hang: 407 ldr sp, _TEXT_BASE /* use 32 words about stack */ 408 bl hang /* hang and never return */ 409#else /* !CONFIG_SPL_BUILD */ 410 .align 5 411undefined_instruction: 412 get_bad_stack 413 bad_save_user_regs 414 bl do_undefined_instruction 415 416 .align 5 417software_interrupt: 418 get_bad_stack_swi 419 bad_save_user_regs 420 bl do_software_interrupt 421 422 .align 5 423prefetch_abort: 424 get_bad_stack 425 bad_save_user_regs 426 bl do_prefetch_abort 427 428 .align 5 429data_abort: 430 get_bad_stack 431 bad_save_user_regs 432 bl do_data_abort 433 434 .align 5 435not_used: 436 get_bad_stack 437 bad_save_user_regs 438 bl do_not_used 439 440#ifdef CONFIG_USE_IRQ 441 442 .align 5 443irq: 444 get_irq_stack 445 irq_save_user_regs 446 bl do_irq 447 irq_restore_user_regs 448 449 .align 5 450fiq: 451 get_fiq_stack 452 /* someone ought to write a more effiction fiq_save_user_regs */ 453 irq_save_user_regs 454 bl do_fiq 455 irq_restore_user_regs 456 457#else 458 459 .align 5 460irq: 461 get_bad_stack 462 bad_save_user_regs 463 bl do_irq 464 465 .align 5 466fiq: 467 get_bad_stack 468 bad_save_user_regs 469 bl do_fiq 470 471#endif 472 .align 5 473#endif /* CONFIG_SPL_BUILD */ 474 475 476/* 477 * Enable MMU to use DCache as DRAM. 478 * 479 * This is useful on PXA25x and PXA26x in early bootstages, where there is no 480 * other possible memory available to hold stack. 481 */ 482#ifdef CONFIG_CPU_PXA25X 483.macro CPWAIT reg 484 mrc p15, 0, \reg, c2, c0, 0 485 mov \reg, \reg 486 sub pc, pc, #4 487.endm 488lock_cache_for_stack: 489 /* Domain access -- enable for all CPs */ 490 ldr r0, =0x0000ffff 491 mcr p15, 0, r0, c3, c0, 0 492 493 /* Point TTBR to MMU table */ 494 ldr r0, =mmutable 495 mcr p15, 0, r0, c2, c0, 0 496 497 /* Kick in MMU, ICache, DCache, BTB */ 498 mrc p15, 0, r0, c1, c0, 0 499 bic r0, #0x1b00 500 bic r0, #0x0087 501 orr r0, #0x1800 502 orr r0, #0x0005 503 mcr p15, 0, r0, c1, c0, 0 504 CPWAIT r0 505 506 /* Unlock Icache, Dcache */ 507 mcr p15, 0, r0, c9, c1, 1 508 mcr p15, 0, r0, c9, c2, 1 509 510 /* Flush Icache, Dcache, BTB */ 511 mcr p15, 0, r0, c7, c7, 0 512 513 /* Unlock I-TLB, D-TLB */ 514 mcr p15, 0, r0, c10, c4, 1 515 mcr p15, 0, r0, c10, c8, 1 516 517 /* Flush TLB */ 518 mcr p15, 0, r0, c8, c7, 0 519 520 /* Allocate 4096 bytes of Dcache as RAM */ 521 522 /* Drain pending loads and stores */ 523 mcr p15, 0, r0, c7, c10, 4 524 525 mov r4, #0x00 526 mov r5, #0x00 527 mov r2, #0x01 528 mcr p15, 0, r0, c9, c2, 0 529 CPWAIT r0 530 531 /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */ 532 mov r0, #128 533 ldr r1, =0xfffff000 534 535alloc: 536 mcr p15, 0, r1, c7, c2, 5 537 /* Drain pending loads and stores */ 538 mcr p15, 0, r0, c7, c10, 4 539 strd r4, [r1], #8 540 strd r4, [r1], #8 541 strd r4, [r1], #8 542 strd r4, [r1], #8 543 subs r0, #0x01 544 bne alloc 545 /* Drain pending loads and stores */ 546 mcr p15, 0, r0, c7, c10, 4 547 mov r2, #0x00 548 mcr p15, 0, r2, c9, c2, 0 549 CPWAIT r0 550 551 mov pc, lr 552 553.section .mmutable, "a" 554mmutable: 555 .align 14 556 /* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */ 557 .set __base, 0 558 .rept 0xfff 559 .word (__base << 20) | 0xc12 560 .set __base, __base + 1 561 .endr 562 563 /* 0xfff00000 : 1:1, cached mapping */ 564 .word (0xfff << 20) | 0x1c1e 565#endif /* CONFIG_CPU_PXA25X */ 566