1/* 2 * armboot - Startup Code for XScale CPU-core 3 * 4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> 7 * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de> 8 * Copyright (C) 2001 Marius Groger <mag@sysgo.de> 9 * Copyright (C) 2002 Alex Zupke <azu@sysgo.de> 10 * Copyright (C) 2002 Gary Jennejohn <garyj@denx.de> 11 * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net> 12 * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de> 13 * Copyright (C) 2003 Kshitij <kshitij@ti.com> 14 * Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com> 15 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> 16 * Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com> 17 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> 18 * 19 * See file CREDITS for list of people who contributed to this 20 * project. 21 * 22 * This program is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU General Public License as 24 * published by the Free Software Foundation; either version 2 of 25 * the License, or (at your option) any later version. 26 * 27 * This program is distributed in the hope that it will be useful, 28 * but WITHOUT ANY WARRANTY; without even the implied warranty of 29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 30 * GNU General Public License for more details. 31 * 32 * You should have received a copy of the GNU General Public License 33 * along with this program; if not, write to the Free Software 34 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 35 * MA 02111-1307 USA 36 */ 37 38#include <asm-offsets.h> 39#include <config.h> 40#include <version.h> 41.globl _start 42_start: b reset 43#ifdef CONFIG_SPL_BUILD 44 ldr pc, _hang 45 ldr pc, _hang 46 ldr pc, _hang 47 ldr pc, _hang 48 ldr pc, _hang 49 ldr pc, _hang 50 ldr pc, _hang 51 52_hang: 53 .word do_hang 54 .word 0x12345678 55 .word 0x12345678 56 .word 0x12345678 57 .word 0x12345678 58 .word 0x12345678 59 .word 0x12345678 60 .word 0x12345678 /* now 16*4=64 */ 61#else 62 ldr pc, _undefined_instruction 63 ldr pc, _software_interrupt 64 ldr pc, _prefetch_abort 65 ldr pc, _data_abort 66 ldr pc, _not_used 67 ldr pc, _irq 68 ldr pc, _fiq 69 70_undefined_instruction: .word undefined_instruction 71_software_interrupt: .word software_interrupt 72_prefetch_abort: .word prefetch_abort 73_data_abort: .word data_abort 74_not_used: .word not_used 75_irq: .word irq 76_fiq: .word fiq 77_pad: .word 0x12345678 /* now 16*4=64 */ 78#endif /* CONFIG_SPL_BUILD */ 79.global _end_vect 80_end_vect: 81 82 .balignl 16,0xdeadbeef 83/* 84 ************************************************************************* 85 * 86 * Startup Code (reset vector) 87 * 88 * do important init only if we don't start from memory! 89 * setup Memory and board specific bits prior to relocation. 90 * relocate armboot to ram 91 * setup stack 92 * 93 ************************************************************************* 94 */ 95 96.globl _TEXT_BASE 97_TEXT_BASE: 98#ifdef CONFIG_SPL_BUILD 99 .word CONFIG_SPL_TEXT_BASE 100#else 101 .word CONFIG_SYS_TEXT_BASE 102#endif 103 104/* 105 * These are defined in the board-specific linker script. 106 * Subtracting _start from them lets the linker put their 107 * relative position in the executable instead of leaving 108 * them null. 109 */ 110.globl _bss_start_ofs 111_bss_start_ofs: 112 .word __bss_start - _start 113 114.globl _bss_end_ofs 115_bss_end_ofs: 116 .word __bss_end__ - _start 117 118.globl _end_ofs 119_end_ofs: 120 .word _end - _start 121 122#ifdef CONFIG_USE_IRQ 123/* IRQ stack memory (calculated at run-time) */ 124.globl IRQ_STACK_START 125IRQ_STACK_START: 126 .word 0x0badc0de 127 128/* IRQ stack memory (calculated at run-time) */ 129.globl FIQ_STACK_START 130FIQ_STACK_START: 131 .word 0x0badc0de 132#endif 133 134/* IRQ stack memory (calculated at run-time) + 8 bytes */ 135.globl IRQ_STACK_START_IN 136IRQ_STACK_START_IN: 137 .word 0x0badc0de 138 139/* 140 * the actual reset code 141 */ 142 143reset: 144 /* 145 * set the cpu to SVC32 mode 146 */ 147 mrs r0,cpsr 148 bic r0,r0,#0x1f 149 orr r0,r0,#0xd3 150 msr cpsr,r0 151 152#ifndef CONFIG_SKIP_LOWLEVEL_INIT 153 bl cpu_init_crit 154#endif 155 156/* Set stackpointer in internal RAM to call board_init_f */ 157call_board_init_f: 158 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 159 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 160 ldr r0, =0x00000000 161 bl board_init_f 162 163/*------------------------------------------------------------------------------*/ 164#ifndef CONFIG_SPL_BUILD 165/* 166 * void relocate_code (addr_sp, gd, addr_moni) 167 * 168 * This "function" does not return, instead it continues in RAM 169 * after relocating the monitor code. 170 * 171 */ 172 .globl relocate_code 173relocate_code: 174 mov r4, r0 /* save addr_sp */ 175 mov r5, r1 /* save addr of gd */ 176 mov r6, r2 /* save addr of destination */ 177 178 /* Set up the stack */ 179stack_setup: 180 mov sp, r4 181 182 adr r0, _start 183 cmp r0, r6 184 beq clear_bss /* skip relocation */ 185 mov r1, r6 /* r1 <- scratch for copy_loop */ 186 ldr r3, _bss_start_ofs 187 add r2, r0, r3 /* r2 <- source end address */ 188 189copy_loop: 190 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 191 stmia r1!, {r9-r10} /* copy to target address [r1] */ 192 cmp r0, r2 /* until source end address [r2] */ 193 blo copy_loop 194 195#ifndef CONFIG_SPL_BUILD 196 /* 197 * fix .rel.dyn relocations 198 */ 199 ldr r0, _TEXT_BASE /* r0 <- Text base */ 200 sub r9, r6, r0 /* r9 <- relocation offset */ 201 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 202 add r10, r10, r0 /* r10 <- sym table in FLASH */ 203 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 204 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 205 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 206 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 207fixloop: 208 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 209 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 210 ldr r1, [r2, #4] 211 and r7, r1, #0xff 212 cmp r7, #23 /* relative fixup? */ 213 beq fixrel 214 cmp r7, #2 /* absolute fixup? */ 215 beq fixabs 216 /* ignore unknown type of fixup */ 217 b fixnext 218fixabs: 219 /* absolute fix: set location to (offset) symbol value */ 220 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 221 add r1, r10, r1 /* r1 <- address of symbol in table */ 222 ldr r1, [r1, #4] /* r1 <- symbol value */ 223 add r1, r1, r9 /* r1 <- relocated sym addr */ 224 b fixnext 225fixrel: 226 /* relative fix: increase location by offset */ 227 ldr r1, [r0] 228 add r1, r1, r9 229fixnext: 230 str r1, [r0] 231 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 232 cmp r2, r3 233 blo fixloop 234#endif 235 236clear_bss: 237#ifndef CONFIG_SPL_BUILD 238 ldr r0, _bss_start_ofs 239 ldr r1, _bss_end_ofs 240 mov r4, r6 /* reloc addr */ 241 add r0, r0, r4 242 add r1, r1, r4 243 mov r2, #0x00000000 /* clear */ 244 245clbss_l:str r2, [r0] /* clear loop... */ 246 add r0, r0, #4 247 cmp r0, r1 248 bne clbss_l 249#endif /* #ifndef CONFIG_SPL_BUILD */ 250 251/* 252 * We are done. Do not return, instead branch to second part of board 253 * initialization, now running from RAM. 254 */ 255#ifdef CONFIG_ONENAND_SPL 256 ldr r0, _onenand_boot_ofs 257 mov pc, r0 258 259_onenand_boot_ofs: 260 .word onenand_boot 261#else 262jump_2_ram: 263 ldr r0, _board_init_r_ofs 264 ldr r1, _TEXT_BASE 265 add lr, r0, r1 266 add lr, lr, r9 267 /* setup parameters for board_init_r */ 268 mov r0, r5 /* gd_t */ 269 mov r1, r6 /* dest_addr */ 270 /* jump to it ... */ 271 mov pc, lr 272 273_board_init_r_ofs: 274 .word board_init_r - _start 275#endif 276 277_rel_dyn_start_ofs: 278 .word __rel_dyn_start - _start 279_rel_dyn_end_ofs: 280 .word __rel_dyn_end - _start 281_dynsym_start_ofs: 282 .word __dynsym_start - _start 283#endif 284/* 285 ************************************************************************* 286 * 287 * CPU_init_critical registers 288 * 289 * setup important registers 290 * setup memory timing 291 * 292 ************************************************************************* 293 */ 294#ifndef CONFIG_SKIP_LOWLEVEL_INIT 295cpu_init_crit: 296 /* 297 * flush v4 I/D caches 298 */ 299 mov r0, #0 300 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 301 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 302 303 /* 304 * disable MMU stuff and caches 305 */ 306 mrc p15, 0, r0, c1, c0, 0 307 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 308 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 309 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 310 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 311 mcr p15, 0, r0, c1, c0, 0 312 313 mov pc, lr /* back to my caller */ 314#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 315 316#ifndef CONFIG_SPL_BUILD 317/* 318 ************************************************************************* 319 * 320 * Interrupt handling 321 * 322 ************************************************************************* 323 */ 324@ 325@ IRQ stack frame. 326@ 327#define S_FRAME_SIZE 72 328 329#define S_OLD_R0 68 330#define S_PSR 64 331#define S_PC 60 332#define S_LR 56 333#define S_SP 52 334 335#define S_IP 48 336#define S_FP 44 337#define S_R10 40 338#define S_R9 36 339#define S_R8 32 340#define S_R7 28 341#define S_R6 24 342#define S_R5 20 343#define S_R4 16 344#define S_R3 12 345#define S_R2 8 346#define S_R1 4 347#define S_R0 0 348 349#define MODE_SVC 0x13 350#define I_BIT 0x80 351 352/* 353 * use bad_save_user_regs for abort/prefetch/undef/swi ... 354 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 355 */ 356 357 .macro bad_save_user_regs 358 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack 359 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 360 361 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack 362 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) 363 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 364 365 add r5, sp, #S_SP 366 mov r1, lr 367 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 368 mov r0, sp @ save current stack into r0 (param register) 369 .endm 370 371 .macro irq_save_user_regs 372 sub sp, sp, #S_FRAME_SIZE 373 stmia sp, {r0 - r12} @ Calling r0-r12 374 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 375 stmdb r8, {sp, lr}^ @ Calling SP, LR 376 str lr, [r8, #0] @ Save calling PC 377 mrs r6, spsr 378 str r6, [r8, #4] @ Save CPSR 379 str r0, [r8, #8] @ Save OLD_R0 380 mov r0, sp 381 .endm 382 383 .macro irq_restore_user_regs 384 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 385 mov r0, r0 386 ldr lr, [sp, #S_PC] @ Get PC 387 add sp, sp, #S_FRAME_SIZE 388 subs pc, lr, #4 @ return & move spsr_svc into cpsr 389 .endm 390 391 .macro get_bad_stack 392 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) 393 394 str lr, [r13] @ save caller lr in position 0 of saved stack 395 mrs lr, spsr @ get the spsr 396 str lr, [r13, #4] @ save spsr in position 1 of saved stack 397 398 mov r13, #MODE_SVC @ prepare SVC-Mode 399 @ msr spsr_c, r13 400 msr spsr, r13 @ switch modes, make sure moves will execute 401 mov lr, pc @ capture return pc 402 movs pc, lr @ jump to next instruction & switch modes. 403 .endm 404 405 .macro get_bad_stack_swi 406 sub r13, r13, #4 @ space on current stack for scratch reg. 407 str r0, [r13] @ save R0's value. 408 ldr r0, IRQ_STACK_START_IN @ get data regions start 409 str lr, [r0] @ save caller lr in position 0 of saved stack 410 mrs r0, spsr @ get the spsr 411 str lr, [r0, #4] @ save spsr in position 1 of saved stack 412 ldr r0, [r13] @ restore r0 413 add r13, r13, #4 @ pop stack entry 414 .endm 415 416 .macro get_irq_stack @ setup IRQ stack 417 ldr sp, IRQ_STACK_START 418 .endm 419 420 .macro get_fiq_stack @ setup FIQ stack 421 ldr sp, FIQ_STACK_START 422 .endm 423#endif /* CONFIG_SPL_BUILD */ 424 425/* 426 * exception handlers 427 */ 428#ifdef CONFIG_SPL_BUILD 429 .align 5 430do_hang: 431 ldr sp, _TEXT_BASE /* use 32 words about stack */ 432 bl hang /* hang and never return */ 433#else /* !CONFIG_SPL_BUILD */ 434 .align 5 435undefined_instruction: 436 get_bad_stack 437 bad_save_user_regs 438 bl do_undefined_instruction 439 440 .align 5 441software_interrupt: 442 get_bad_stack_swi 443 bad_save_user_regs 444 bl do_software_interrupt 445 446 .align 5 447prefetch_abort: 448 get_bad_stack 449 bad_save_user_regs 450 bl do_prefetch_abort 451 452 .align 5 453data_abort: 454 get_bad_stack 455 bad_save_user_regs 456 bl do_data_abort 457 458 .align 5 459not_used: 460 get_bad_stack 461 bad_save_user_regs 462 bl do_not_used 463 464#ifdef CONFIG_USE_IRQ 465 466 .align 5 467irq: 468 get_irq_stack 469 irq_save_user_regs 470 bl do_irq 471 irq_restore_user_regs 472 473 .align 5 474fiq: 475 get_fiq_stack 476 /* someone ought to write a more effiction fiq_save_user_regs */ 477 irq_save_user_regs 478 bl do_fiq 479 irq_restore_user_regs 480 481#else 482 483 .align 5 484irq: 485 get_bad_stack 486 bad_save_user_regs 487 bl do_irq 488 489 .align 5 490fiq: 491 get_bad_stack 492 bad_save_user_regs 493 bl do_fiq 494 495#endif 496 .align 5 497#endif /* CONFIG_SPL_BUILD */ 498