1 /* 2 * (C) Copyright 2014 - 2015 Xilinx, Inc. 3 * Michal Simek <michal.simek@xilinx.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/arch/hardware.h> 10 #include <asm/arch/sys_proto.h> 11 #include <asm/armv8/mmu.h> 12 #include <asm/io.h> 13 14 #define ZYNQ_SILICON_VER_MASK 0xF000 15 #define ZYNQ_SILICON_VER_SHIFT 12 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 static struct mm_region zynqmp_mem_map[] = { 20 { 21 .virt = 0x0UL, 22 .phys = 0x0UL, 23 .size = 0x80000000UL, 24 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 25 PTE_BLOCK_INNER_SHARE 26 }, { 27 .virt = 0x80000000UL, 28 .phys = 0x80000000UL, 29 .size = 0x70000000UL, 30 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 31 PTE_BLOCK_NON_SHARE | 32 PTE_BLOCK_PXN | PTE_BLOCK_UXN 33 }, { 34 .virt = 0xf8000000UL, 35 .phys = 0xf8000000UL, 36 .size = 0x07e00000UL, 37 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 38 PTE_BLOCK_NON_SHARE | 39 PTE_BLOCK_PXN | PTE_BLOCK_UXN 40 }, { 41 .virt = 0xffe00000UL, 42 .phys = 0xffe00000UL, 43 .size = 0x00200000UL, 44 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 45 PTE_BLOCK_INNER_SHARE 46 }, { 47 .virt = 0x400000000UL, 48 .phys = 0x400000000UL, 49 .size = 0x200000000UL, 50 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 51 PTE_BLOCK_NON_SHARE | 52 PTE_BLOCK_PXN | PTE_BLOCK_UXN 53 }, { 54 .virt = 0x600000000UL, 55 .phys = 0x600000000UL, 56 .size = 0x800000000UL, 57 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 58 PTE_BLOCK_INNER_SHARE 59 }, { 60 .virt = 0xe00000000UL, 61 .phys = 0xe00000000UL, 62 .size = 0xf200000000UL, 63 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 64 PTE_BLOCK_NON_SHARE | 65 PTE_BLOCK_PXN | PTE_BLOCK_UXN 66 }, { 67 /* List terminator */ 68 0, 69 } 70 }; 71 struct mm_region *mem_map = zynqmp_mem_map; 72 73 u64 get_page_table_size(void) 74 { 75 return 0x14000; 76 } 77 78 static unsigned int zynqmp_get_silicon_version_secure(void) 79 { 80 u32 ver; 81 82 ver = readl(&csu_base->version); 83 ver &= ZYNQMP_SILICON_VER_MASK; 84 ver >>= ZYNQMP_SILICON_VER_SHIFT; 85 86 return ver; 87 } 88 89 unsigned int zynqmp_get_silicon_version(void) 90 { 91 if (current_el() == 3) 92 return zynqmp_get_silicon_version_secure(); 93 94 gd->cpu_clk = get_tbclk(); 95 96 switch (gd->cpu_clk) { 97 case 0 ... 1000000: 98 return ZYNQMP_CSU_VERSION_VELOCE; 99 case 50000000: 100 return ZYNQMP_CSU_VERSION_QEMU; 101 case 4000000: 102 return ZYNQMP_CSU_VERSION_EP108; 103 } 104 105 return ZYNQMP_CSU_VERSION_SILICON; 106 } 107