1 /* 2 * (C) Copyright 2014 - 2015 Xilinx, Inc. 3 * Michal Simek <michal.simek@xilinx.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/arch/hardware.h> 10 #include <asm/arch/sys_proto.h> 11 #include <asm/io.h> 12 13 #define ZYNQ_SILICON_VER_MASK 0xF000 14 #define ZYNQ_SILICON_VER_SHIFT 12 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 unsigned int zynqmp_get_silicon_version(void) 19 { 20 gd->cpu_clk = get_tbclk(); 21 22 switch (gd->cpu_clk) { 23 case 0 ... 1000000: 24 return ZYNQMP_CSU_VERSION_VELOCE; 25 case 50000000: 26 return ZYNQMP_CSU_VERSION_QEMU; 27 } 28 29 return ZYNQMP_CSU_VERSION_EP108; 30 } 31 32 #ifndef CONFIG_SYS_DCACHE_OFF 33 #include <asm/armv8/mmu.h> 34 35 #define SECTION_SHIFT_L1 30UL 36 #define SECTION_SHIFT_L2 21UL 37 #define BLOCK_SIZE_L0 0x8000000000UL 38 #define BLOCK_SIZE_L1 (1 << SECTION_SHIFT_L1) 39 #define BLOCK_SIZE_L2 (1 << SECTION_SHIFT_L2) 40 41 #define TCR_TG1_4K (1 << 31) 42 #define TCR_EPD1_DISABLE (1 << 23) 43 #define ZYNQMO_VA_BITS 40 44 #define ZYNQMP_TCR TCR_TG1_4K | \ 45 TCR_EPD1_DISABLE | \ 46 TCR_SHARED_OUTER | \ 47 TCR_SHARED_INNER | \ 48 TCR_IRGN_WBWA | \ 49 TCR_ORGN_WBWA | \ 50 TCR_T0SZ(ZYNQMO_VA_BITS) 51 52 #define MEMORY_ATTR PMD_SECT_AF | PMD_SECT_INNER_SHARE | \ 53 PMD_ATTRINDX(MT_NORMAL) | \ 54 PMD_TYPE_SECT 55 #define DEVICE_ATTR PMD_SECT_AF | PMD_SECT_PXN | \ 56 PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_NGNRNE) | \ 57 PMD_TYPE_SECT 58 59 /* 4K size is required to place 512 entries in each level */ 60 #define TLB_TABLE_SIZE 0x1000 61 62 struct attr_tbl { 63 u32 num; 64 u64 attr; 65 }; 66 67 static struct attr_tbl attr_tbll1t0[4] = { {16, 0x0}, 68 {8, DEVICE_ATTR}, 69 {32, MEMORY_ATTR}, 70 {456, DEVICE_ATTR} 71 }; 72 static struct attr_tbl attr_tbll2t3[4] = { {0x180, DEVICE_ATTR}, 73 {0x40, 0x0}, 74 {0x3F, DEVICE_ATTR}, 75 {0x1, MEMORY_ATTR} 76 }; 77 78 /* 79 * This mmu table looks as below 80 * Level 0 table contains two entries to 512GB sizes. One is Level1 Table 0 81 * and other Level1 Table1. 82 * Level1 Table0 contains entries for each 1GB from 0 to 511GB. 83 * Level1 Table1 contains entries for each 1GB from 512GB to 1TB. 84 * Level2 Table0, Level2 Table1, Level2 Table2 and Level2 Table3 contains 85 * entries for each 2MB starting from 0GB, 1GB, 2GB and 3GB respectively. 86 */ 87 static void zynqmp_mmu_setup(void) 88 { 89 int el; 90 u32 index_attr; 91 u64 i, section_l1t0, section_l1t1; 92 u64 section_l2t0, section_l2t1, section_l2t2, section_l2t3; 93 u64 *level0_table = (u64 *)gd->arch.tlb_addr; 94 u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + TLB_TABLE_SIZE); 95 u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + (2 * TLB_TABLE_SIZE)); 96 u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE)); 97 u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + (4 * TLB_TABLE_SIZE)); 98 u64 *level2_table_2 = (u64 *)(gd->arch.tlb_addr + (5 * TLB_TABLE_SIZE)); 99 u64 *level2_table_3 = (u64 *)(gd->arch.tlb_addr + (6 * TLB_TABLE_SIZE)); 100 101 level0_table[0] = 102 (u64)level1_table_0 | PMD_TYPE_TABLE; 103 level0_table[1] = 104 (u64)level1_table_1 | PMD_TYPE_TABLE; 105 106 /* 107 * set level 1 table 0, covering 0 to 512GB 108 * set level 1 table 1, covering 512GB to 1TB 109 */ 110 section_l1t0 = 0; 111 section_l1t1 = BLOCK_SIZE_L0; 112 113 index_attr = 0; 114 for (i = 0; i < 512; i++) { 115 level1_table_0[i] = section_l1t0; 116 level1_table_0[i] |= attr_tbll1t0[index_attr].attr; 117 attr_tbll1t0[index_attr].num--; 118 if (attr_tbll1t0[index_attr].num == 0) 119 index_attr++; 120 level1_table_1[i] = section_l1t1; 121 level1_table_1[i] |= DEVICE_ATTR; 122 section_l1t0 += BLOCK_SIZE_L1; 123 section_l1t1 += BLOCK_SIZE_L1; 124 } 125 126 level1_table_0[0] = 127 (u64)level2_table_0 | PMD_TYPE_TABLE; 128 level1_table_0[1] = 129 (u64)level2_table_1 | PMD_TYPE_TABLE; 130 level1_table_0[2] = 131 (u64)level2_table_2 | PMD_TYPE_TABLE; 132 level1_table_0[3] = 133 (u64)level2_table_3 | PMD_TYPE_TABLE; 134 135 section_l2t0 = 0; 136 section_l2t1 = section_l2t0 + BLOCK_SIZE_L1; /* 1GB */ 137 section_l2t2 = section_l2t1 + BLOCK_SIZE_L1; /* 2GB */ 138 section_l2t3 = section_l2t2 + BLOCK_SIZE_L1; /* 3GB */ 139 140 index_attr = 0; 141 142 for (i = 0; i < 512; i++) { 143 level2_table_0[i] = section_l2t0 | MEMORY_ATTR; 144 level2_table_1[i] = section_l2t1 | MEMORY_ATTR; 145 level2_table_2[i] = section_l2t2 | DEVICE_ATTR; 146 level2_table_3[i] = section_l2t3 | 147 attr_tbll2t3[index_attr].attr; 148 attr_tbll2t3[index_attr].num--; 149 if (attr_tbll2t3[index_attr].num == 0) 150 index_attr++; 151 section_l2t0 += BLOCK_SIZE_L2; 152 section_l2t1 += BLOCK_SIZE_L2; 153 section_l2t2 += BLOCK_SIZE_L2; 154 section_l2t3 += BLOCK_SIZE_L2; 155 } 156 157 /* flush new MMU table */ 158 flush_dcache_range(gd->arch.tlb_addr, 159 gd->arch.tlb_addr + gd->arch.tlb_size); 160 161 /* point TTBR to the new table */ 162 el = current_el(); 163 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, 164 ZYNQMP_TCR, MEMORY_ATTRIBUTES); 165 166 set_sctlr(get_sctlr() | CR_M); 167 } 168 169 int arch_cpu_init(void) 170 { 171 icache_enable(); 172 __asm_invalidate_dcache_all(); 173 __asm_invalidate_tlb_all(); 174 return 0; 175 } 176 177 /* 178 * This function is called from lib/board.c. 179 * It recreates MMU table in main memory. MMU and d-cache are enabled earlier. 180 * There is no need to disable d-cache for this operation. 181 */ 182 void enable_caches(void) 183 { 184 /* The data cache is not active unless the mmu is enabled */ 185 if (!(get_sctlr() & CR_M)) { 186 invalidate_dcache_all(); 187 __asm_invalidate_tlb_all(); 188 zynqmp_mmu_setup(); 189 } 190 puts("Enabling Caches...\n"); 191 192 set_sctlr(get_sctlr() | CR_C); 193 } 194 195 u64 *arch_get_page_table(void) 196 { 197 return (u64 *)(gd->arch.tlb_addr + 0x3000); 198 } 199 #endif 200