1 /* 2 * (C) Copyright 2014 - 2015 Xilinx, Inc. 3 * Michal Simek <michal.simek@xilinx.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/arch/hardware.h> 10 #include <asm/arch/sys_proto.h> 11 #include <asm/armv8/mmu.h> 12 #include <asm/io.h> 13 14 #define ZYNQ_SILICON_VER_MASK 0xF000 15 #define ZYNQ_SILICON_VER_SHIFT 12 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 static struct mm_region zynqmp_mem_map[] = { 20 { 21 .base = 0x0UL, 22 .size = 0x80000000UL, 23 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 24 PTE_BLOCK_INNER_SHARE 25 }, { 26 .base = 0x80000000UL, 27 .size = 0x70000000UL, 28 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 29 PTE_BLOCK_NON_SHARE | 30 PTE_BLOCK_PXN | PTE_BLOCK_UXN 31 }, { 32 .base = 0xf8000000UL, 33 .size = 0x07e00000UL, 34 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 35 PTE_BLOCK_NON_SHARE | 36 PTE_BLOCK_PXN | PTE_BLOCK_UXN 37 }, { 38 .base = 0xffe00000UL, 39 .size = 0x00200000UL, 40 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 41 PTE_BLOCK_INNER_SHARE 42 }, { 43 .base = 0x400000000UL, 44 .size = 0x200000000UL, 45 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 46 PTE_BLOCK_NON_SHARE | 47 PTE_BLOCK_PXN | PTE_BLOCK_UXN 48 }, { 49 .base = 0x600000000UL, 50 .size = 0x800000000UL, 51 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 52 PTE_BLOCK_INNER_SHARE 53 }, { 54 .base = 0xe00000000UL, 55 .size = 0xf200000000UL, 56 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 57 PTE_BLOCK_NON_SHARE | 58 PTE_BLOCK_PXN | PTE_BLOCK_UXN 59 }, { 60 /* List terminator */ 61 0, 62 } 63 }; 64 struct mm_region *mem_map = zynqmp_mem_map; 65 66 static unsigned int zynqmp_get_silicon_version_secure(void) 67 { 68 u32 ver; 69 70 ver = readl(&csu_base->version); 71 ver &= ZYNQMP_SILICON_VER_MASK; 72 ver >>= ZYNQMP_SILICON_VER_SHIFT; 73 74 return ver; 75 } 76 77 unsigned int zynqmp_get_silicon_version(void) 78 { 79 if (current_el() == 3) 80 return zynqmp_get_silicon_version_secure(); 81 82 gd->cpu_clk = get_tbclk(); 83 84 switch (gd->cpu_clk) { 85 case 0 ... 1000000: 86 return ZYNQMP_CSU_VERSION_VELOCE; 87 case 50000000: 88 return ZYNQMP_CSU_VERSION_QEMU; 89 case 4000000: 90 return ZYNQMP_CSU_VERSION_EP108; 91 } 92 93 return ZYNQMP_CSU_VERSION_SILICON; 94 } 95