1 /* 2 * (C) Copyright 2014 - 2015 Xilinx, Inc. 3 * Michal Simek <michal.simek@xilinx.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/arch/hardware.h> 10 #include <asm/arch/sys_proto.h> 11 #include <asm/io.h> 12 13 #define ZYNQ_SILICON_VER_MASK 0xF000 14 #define ZYNQ_SILICON_VER_SHIFT 12 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 static unsigned int zynqmp_get_silicon_version_secure(void) 19 { 20 u32 ver; 21 22 ver = readl(&csu_base->version); 23 ver &= ZYNQMP_SILICON_VER_MASK; 24 ver >>= ZYNQMP_SILICON_VER_SHIFT; 25 26 return ver; 27 } 28 29 unsigned int zynqmp_get_silicon_version(void) 30 { 31 if (current_el() == 3) 32 return zynqmp_get_silicon_version_secure(); 33 34 gd->cpu_clk = get_tbclk(); 35 36 switch (gd->cpu_clk) { 37 case 0 ... 1000000: 38 return ZYNQMP_CSU_VERSION_VELOCE; 39 case 50000000: 40 return ZYNQMP_CSU_VERSION_QEMU; 41 } 42 43 return ZYNQMP_CSU_VERSION_EP108; 44 } 45 46 #ifndef CONFIG_SYS_DCACHE_OFF 47 #include <asm/armv8/mmu.h> 48 49 #define SECTION_SHIFT_L1 30UL 50 #define SECTION_SHIFT_L2 21UL 51 #define BLOCK_SIZE_L0 0x8000000000UL 52 #define BLOCK_SIZE_L1 (1 << SECTION_SHIFT_L1) 53 #define BLOCK_SIZE_L2 (1 << SECTION_SHIFT_L2) 54 55 #define TCR_TG1_4K (1 << 31) 56 #define TCR_EPD1_DISABLE (1 << 23) 57 #define ZYNQMO_VA_BITS 40 58 #define ZYNQMP_TCR TCR_TG1_4K | \ 59 TCR_EPD1_DISABLE | \ 60 TCR_SHARED_OUTER | \ 61 TCR_SHARED_INNER | \ 62 TCR_IRGN_WBWA | \ 63 TCR_ORGN_WBWA | \ 64 TCR_T0SZ(ZYNQMO_VA_BITS) 65 66 #define MEMORY_ATTR PMD_SECT_AF | PMD_SECT_INNER_SHARE | \ 67 PMD_ATTRINDX(MT_NORMAL) | \ 68 PMD_TYPE_SECT 69 #define DEVICE_ATTR PMD_SECT_AF | PMD_SECT_PXN | \ 70 PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_NGNRNE) | \ 71 PMD_TYPE_SECT 72 73 /* 4K size is required to place 512 entries in each level */ 74 #define TLB_TABLE_SIZE 0x1000 75 76 struct attr_tbl { 77 u32 num; 78 u64 attr; 79 }; 80 81 static struct attr_tbl attr_tbll1t0[4] = { {16, 0x0}, 82 {8, DEVICE_ATTR}, 83 {32, MEMORY_ATTR}, 84 {456, DEVICE_ATTR} 85 }; 86 static struct attr_tbl attr_tbll2t3[4] = { {0x180, DEVICE_ATTR}, 87 {0x40, 0x0}, 88 {0x3F, DEVICE_ATTR}, 89 {0x1, MEMORY_ATTR} 90 }; 91 92 /* 93 * This mmu table looks as below 94 * Level 0 table contains two entries to 512GB sizes. One is Level1 Table 0 95 * and other Level1 Table1. 96 * Level1 Table0 contains entries for each 1GB from 0 to 511GB. 97 * Level1 Table1 contains entries for each 1GB from 512GB to 1TB. 98 * Level2 Table0, Level2 Table1, Level2 Table2 and Level2 Table3 contains 99 * entries for each 2MB starting from 0GB, 1GB, 2GB and 3GB respectively. 100 */ 101 static void zynqmp_mmu_setup(void) 102 { 103 int el; 104 u32 index_attr; 105 u64 i, section_l1t0, section_l1t1; 106 u64 section_l2t0, section_l2t1, section_l2t2, section_l2t3; 107 u64 *level0_table = (u64 *)gd->arch.tlb_addr; 108 u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + TLB_TABLE_SIZE); 109 u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + (2 * TLB_TABLE_SIZE)); 110 u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE)); 111 u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + (4 * TLB_TABLE_SIZE)); 112 u64 *level2_table_2 = (u64 *)(gd->arch.tlb_addr + (5 * TLB_TABLE_SIZE)); 113 u64 *level2_table_3 = (u64 *)(gd->arch.tlb_addr + (6 * TLB_TABLE_SIZE)); 114 115 level0_table[0] = 116 (u64)level1_table_0 | PMD_TYPE_TABLE; 117 level0_table[1] = 118 (u64)level1_table_1 | PMD_TYPE_TABLE; 119 120 /* 121 * set level 1 table 0, covering 0 to 512GB 122 * set level 1 table 1, covering 512GB to 1TB 123 */ 124 section_l1t0 = 0; 125 section_l1t1 = BLOCK_SIZE_L0; 126 127 index_attr = 0; 128 for (i = 0; i < 512; i++) { 129 level1_table_0[i] = section_l1t0; 130 level1_table_0[i] |= attr_tbll1t0[index_attr].attr; 131 attr_tbll1t0[index_attr].num--; 132 if (attr_tbll1t0[index_attr].num == 0) 133 index_attr++; 134 level1_table_1[i] = section_l1t1; 135 level1_table_1[i] |= DEVICE_ATTR; 136 section_l1t0 += BLOCK_SIZE_L1; 137 section_l1t1 += BLOCK_SIZE_L1; 138 } 139 140 level1_table_0[0] = 141 (u64)level2_table_0 | PMD_TYPE_TABLE; 142 level1_table_0[1] = 143 (u64)level2_table_1 | PMD_TYPE_TABLE; 144 level1_table_0[2] = 145 (u64)level2_table_2 | PMD_TYPE_TABLE; 146 level1_table_0[3] = 147 (u64)level2_table_3 | PMD_TYPE_TABLE; 148 149 section_l2t0 = 0; 150 section_l2t1 = section_l2t0 + BLOCK_SIZE_L1; /* 1GB */ 151 section_l2t2 = section_l2t1 + BLOCK_SIZE_L1; /* 2GB */ 152 section_l2t3 = section_l2t2 + BLOCK_SIZE_L1; /* 3GB */ 153 154 index_attr = 0; 155 156 for (i = 0; i < 512; i++) { 157 level2_table_0[i] = section_l2t0 | MEMORY_ATTR; 158 level2_table_1[i] = section_l2t1 | MEMORY_ATTR; 159 level2_table_2[i] = section_l2t2 | DEVICE_ATTR; 160 level2_table_3[i] = section_l2t3 | 161 attr_tbll2t3[index_attr].attr; 162 attr_tbll2t3[index_attr].num--; 163 if (attr_tbll2t3[index_attr].num == 0) 164 index_attr++; 165 section_l2t0 += BLOCK_SIZE_L2; 166 section_l2t1 += BLOCK_SIZE_L2; 167 section_l2t2 += BLOCK_SIZE_L2; 168 section_l2t3 += BLOCK_SIZE_L2; 169 } 170 171 /* flush new MMU table */ 172 flush_dcache_range(gd->arch.tlb_addr, 173 gd->arch.tlb_addr + gd->arch.tlb_size); 174 175 /* point TTBR to the new table */ 176 el = current_el(); 177 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, 178 ZYNQMP_TCR, MEMORY_ATTRIBUTES); 179 180 set_sctlr(get_sctlr() | CR_M); 181 } 182 183 int arch_cpu_init(void) 184 { 185 icache_enable(); 186 __asm_invalidate_dcache_all(); 187 __asm_invalidate_tlb_all(); 188 return 0; 189 } 190 191 /* 192 * This function is called from lib/board.c. 193 * It recreates MMU table in main memory. MMU and d-cache are enabled earlier. 194 * There is no need to disable d-cache for this operation. 195 */ 196 void enable_caches(void) 197 { 198 /* The data cache is not active unless the mmu is enabled */ 199 if (!(get_sctlr() & CR_M)) { 200 invalidate_dcache_all(); 201 __asm_invalidate_tlb_all(); 202 zynqmp_mmu_setup(); 203 } 204 puts("Enabling Caches...\n"); 205 206 set_sctlr(get_sctlr() | CR_C); 207 } 208 209 u64 *arch_get_page_table(void) 210 { 211 return (u64 *)(gd->arch.tlb_addr + 0x3000); 212 } 213 #endif 214