1 /* 2 * (C) Copyright 2014 - 2015 Xilinx, Inc. 3 * Michal Simek <michal.simek@xilinx.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/arch/hardware.h> 10 #include <asm/arch/sys_proto.h> 11 12 DECLARE_GLOBAL_DATA_PTR; 13 14 unsigned long get_uart_clk(int dev_id) 15 { 16 u32 ver = zynqmp_get_silicon_version(); 17 18 switch (ver) { 19 case ZYNQMP_CSU_VERSION_EP108: 20 return 25000000; 21 } 22 23 return 133000000; 24 } 25 26 #ifdef CONFIG_CLOCKS 27 /** 28 * set_cpu_clk_info() - Initialize clock framework 29 * Always returns zero. 30 * 31 * This function is called from common code after relocation and sets up the 32 * clock framework. The framework must not be used before this function had been 33 * called. 34 */ 35 int set_cpu_clk_info(void) 36 { 37 gd->cpu_clk = get_tbclk(); 38 39 /* Support Veloce to show at least 1MHz via bdi */ 40 if (gd->cpu_clk > 1000000) 41 gd->bd->bi_arm_freq = gd->cpu_clk / 1000000; 42 else 43 gd->bd->bi_arm_freq = 1; 44 45 gd->bd->bi_dsp_freq = 0; 46 47 return 0; 48 } 49 #endif 50