1 /* 2 * (C) Copyright 2014 - 2015 Xilinx, Inc. 3 * Michal Simek <michal.simek@xilinx.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/arch/clk.h> 10 #include <asm/arch/hardware.h> 11 #include <asm/arch/sys_proto.h> 12 13 DECLARE_GLOBAL_DATA_PTR; 14 15 unsigned long get_uart_clk(int dev_id) 16 { 17 u32 ver = zynqmp_get_silicon_version(); 18 19 switch (ver) { 20 case ZYNQMP_CSU_VERSION_VELOCE: 21 return 48000; 22 case ZYNQMP_CSU_VERSION_EP108: 23 return 25000000; 24 } 25 26 return 133000000; 27 } 28 29 #ifdef CONFIG_CLOCKS 30 /** 31 * set_cpu_clk_info() - Initialize clock framework 32 * Always returns zero. 33 * 34 * This function is called from common code after relocation and sets up the 35 * clock framework. The framework must not be used before this function had been 36 * called. 37 */ 38 int set_cpu_clk_info(void) 39 { 40 gd->cpu_clk = get_tbclk(); 41 42 /* Support Veloce to show at least 1MHz via bdi */ 43 if (gd->cpu_clk > 1000000) 44 gd->bd->bi_arm_freq = gd->cpu_clk / 1000000; 45 else 46 gd->bd->bi_arm_freq = 1; 47 48 gd->bd->bi_dsp_freq = 0; 49 50 return 0; 51 } 52 #endif 53