1 /* 2 * (C) Copyright 2014 - 2015 Xilinx, Inc. 3 * Michal Simek <michal.simek@xilinx.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/arch/clk.h> 10 #include <asm/arch/hardware.h> 11 #include <asm/arch/sys_proto.h> 12 13 DECLARE_GLOBAL_DATA_PTR; 14 15 unsigned long get_uart_clk(int dev_id) 16 { 17 u32 ver = zynqmp_get_silicon_version(); 18 19 switch (ver) { 20 case ZYNQMP_CSU_VERSION_VELOCE: 21 return 48000; 22 case ZYNQMP_CSU_VERSION_EP108: 23 return 25000000; 24 case ZYNQMP_CSU_VERSION_QEMU: 25 return 133000000; 26 } 27 28 return 100000000; 29 } 30 31 unsigned long zynqmp_get_system_timer_freq(void) 32 { 33 u32 ver = zynqmp_get_silicon_version(); 34 35 switch (ver) { 36 case ZYNQMP_CSU_VERSION_VELOCE: 37 return 10000; 38 case ZYNQMP_CSU_VERSION_EP108: 39 return 4000000; 40 case ZYNQMP_CSU_VERSION_QEMU: 41 return 50000000; 42 } 43 44 return 100000000; 45 } 46 47 #ifdef CONFIG_CLOCKS 48 /** 49 * set_cpu_clk_info() - Initialize clock framework 50 * Always returns zero. 51 * 52 * This function is called from common code after relocation and sets up the 53 * clock framework. The framework must not be used before this function had been 54 * called. 55 */ 56 int set_cpu_clk_info(void) 57 { 58 gd->cpu_clk = get_tbclk(); 59 60 /* Support Veloce to show at least 1MHz via bdi */ 61 if (gd->cpu_clk > 1000000) 62 gd->bd->bi_arm_freq = gd->cpu_clk / 1000000; 63 else 64 gd->bd->bi_arm_freq = 1; 65 66 gd->bd->bi_dsp_freq = 0; 67 68 return 0; 69 } 70 #endif 71