1 /* 2 * (C) Copyright 2014 - 2015 Xilinx, Inc. 3 * Michal Simek <michal.simek@xilinx.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/arch/clk.h> 10 #include <asm/arch/hardware.h> 11 #include <asm/arch/sys_proto.h> 12 13 DECLARE_GLOBAL_DATA_PTR; 14 15 unsigned long get_uart_clk(int dev_id) 16 { 17 u32 ver = zynqmp_get_silicon_version(); 18 19 switch (ver) { 20 case ZYNQMP_CSU_VERSION_VELOCE: 21 return 48000; 22 case ZYNQMP_CSU_VERSION_EP108: 23 return 25000000; 24 } 25 26 return 133000000; 27 } 28 29 unsigned long zynqmp_get_system_timer_freq(void) 30 { 31 u32 ver = zynqmp_get_silicon_version(); 32 33 switch (ver) { 34 case ZYNQMP_CSU_VERSION_VELOCE: 35 return 10000; 36 case ZYNQMP_CSU_VERSION_EP108: 37 return 4000000; 38 case ZYNQMP_CSU_VERSION_QEMU: 39 return 50000000; 40 } 41 42 return 100000000; 43 } 44 45 #ifdef CONFIG_CLOCKS 46 /** 47 * set_cpu_clk_info() - Initialize clock framework 48 * Always returns zero. 49 * 50 * This function is called from common code after relocation and sets up the 51 * clock framework. The framework must not be used before this function had been 52 * called. 53 */ 54 int set_cpu_clk_info(void) 55 { 56 gd->cpu_clk = get_tbclk(); 57 58 /* Support Veloce to show at least 1MHz via bdi */ 59 if (gd->cpu_clk > 1000000) 60 gd->bd->bi_arm_freq = gd->cpu_clk / 1000000; 61 else 62 gd->bd->bi_arm_freq = 1; 63 64 gd->bd->bi_dsp_freq = 0; 65 66 return 0; 67 } 68 #endif 69