1/* 2 * (C) Copyright 2013 3 * David Feng <fenghua@phytium.com.cn> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8#include <asm-offsets.h> 9#include <config.h> 10#include <linux/linkage.h> 11#include <asm/macro.h> 12#include <asm/armv8/mmu.h> 13 14/************************************************************************* 15 * 16 * Startup Code (reset vector) 17 * 18 *************************************************************************/ 19 20.globl _start 21_start: 22#ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK 23/* 24 * Various SoCs need something special and SoC-specific up front in 25 * order to boot, allow them to set that in their boot0.h file and then 26 * use it here. 27 */ 28#include <asm/arch/boot0.h> 29#else 30 b reset 31#endif 32 33#if !CONFIG_IS_ENABLED(TINY_FRAMEWORK) 34 .align 3 35 36.globl _TEXT_BASE 37_TEXT_BASE: 38#if defined(CONFIG_SPL_BUILD) 39 .quad CONFIG_SPL_TEXT_BASE 40#else 41 .quad CONFIG_SYS_TEXT_BASE 42#endif 43 44/* 45 * These are defined in the linker script. 46 */ 47.globl _end_ofs 48_end_ofs: 49 .quad _end - _start 50 51.globl _bss_start_ofs 52_bss_start_ofs: 53 .quad __bss_start - _start 54 55.globl _bss_end_ofs 56_bss_end_ofs: 57 .quad __bss_end - _start 58 59reset: 60 /* Allow the board to save important registers */ 61 b save_boot_params 62.globl save_boot_params_ret 63save_boot_params_ret: 64 65#if CONFIG_POSITION_INDEPENDENT 66 /* 67 * Fix .rela.dyn relocations. This allows U-Boot to be loaded to and 68 * executed at a different address than it was linked at. 69 */ 70pie_fixup: 71 adr x0, _start /* x0 <- Runtime value of _start */ 72 ldr x1, _TEXT_BASE /* x1 <- Linked value of _start */ 73 sub x9, x0, x1 /* x9 <- Run-vs-link offset */ 74 adr x2, __rel_dyn_start /* x2 <- Runtime &__rel_dyn_start */ 75 adr x3, __rel_dyn_end /* x3 <- Runtime &__rel_dyn_end */ 76pie_fix_loop: 77 ldp x0, x1, [x2], #16 /* (x0, x1) <- (Link location, fixup) */ 78 ldr x4, [x2], #8 /* x4 <- addend */ 79 cmp w1, #1027 /* relative fixup? */ 80 bne pie_skip_reloc 81 /* relative fix: store addend plus offset at dest location */ 82 add x0, x0, x9 83 add x4, x4, x9 84 str x4, [x0] 85pie_skip_reloc: 86 cmp x2, x3 87 b.lo pie_fix_loop 88pie_fixup_done: 89#endif 90 91#ifdef CONFIG_SYS_RESET_SCTRL 92 bl reset_sctrl 93#endif 94 /* 95 * Could be EL3/EL2/EL1, Initial State: 96 * Little Endian, MMU Disabled, i/dCache Disabled 97 */ 98 adr x0, vectors 99 switch_el x1, 3f, 2f, 1f 1003: msr vbar_el3, x0 101 mrs x0, scr_el3 102 orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */ 103 msr scr_el3, x0 104 msr cptr_el3, xzr /* Enable FP/SIMD */ 105#ifdef COUNTER_FREQUENCY 106 ldr x0, =COUNTER_FREQUENCY 107 msr cntfrq_el0, x0 /* Initialize CNTFRQ */ 108#endif 109 b 0f 1102: msr vbar_el2, x0 111 mov x0, #0x33ff 112 msr cptr_el2, x0 /* Enable FP/SIMD */ 113 b 0f 1141: msr vbar_el1, x0 115 mov x0, #3 << 20 116 msr cpacr_el1, x0 /* Enable FP/SIMD */ 1170: 118 119 /* 120 * Enable instruction cache (if required), stack pointer, 121 * data access alignment checks and SError. 122 */ 123#ifndef CONFIG_SYS_ICACHE_OFF 124 mov x1, #CR_I 125#else 126 mov x1, #0 127#endif 128 switch_el x2, 3f, 2f, 1f 1293: mrs x0, sctlr_el3 130 orr x0, x0, x1 131 msr sctlr_el3, x0 132#ifndef CONFIG_SUPPORT_USBPLUG 133 msr daifclr, #4 /* Enable SError. SCR_EL3.EA=1 was already set in start.S */ 134#endif 135 b 0f 1362: mrs x0, sctlr_el2 137 orr x0, x0, x1 138 msr sctlr_el2, x0 139 140 mrs x0, hcr_el2 141 orr x0, x0, #HCR_EL2_TGE 142 orr x0, x0, #HCR_EL2_AMO 143#if CONFIG_IS_ENABLED(IRQ) 144 orr x0, x0, #HCR_EL2_IMO 145#endif 146 msr hcr_el2, x0 147 msr daifclr, #4 148 b 0f 1491: mrs x0, sctlr_el1 150 orr x0, x0, x1 151 msr sctlr_el1, x0 152 msr daifclr, #4 1530: 154 isb 155 156 /* 157 * Enable SMPEN bit for coherency. 158 * This register is not architectural but at the moment 159 * this bit should be set for A53/A57/A72. 160 */ 161#ifdef CONFIG_ARMV8_SET_SMPEN 162 switch_el x1, 3f, 1f, 1f 1633: 164 mrs x0, S3_1_c15_c2_1 /* cpuectlr_el1 */ 165 orr x0, x0, #0x40 166 msr S3_1_c15_c2_1, x0 1671: 168#endif 169 170 /* Apply ARM core specific erratas */ 171 bl apply_core_errata 172 173 /* 174 * Cache/BPB/TLB Invalidate 175 * i-cache is invalidated before enabled in icache_enable() 176 * tlb is invalidated before mmu is enabled in dcache_enable() 177 * d-cache is invalidated before enabled in dcache_enable() 178 */ 179 180 /* Processor specific initialization */ 181 bl lowlevel_init 182 183#if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD) 184 branch_if_master x0, x1, master_cpu 185 b spin_table_secondary_jump 186 /* never return */ 187#elif defined(CONFIG_ARMV8_MULTIENTRY) 188 branch_if_master x0, x1, master_cpu 189 190 /* 191 * Slave CPUs 192 */ 193slave_cpu: 194 wfe 195 ldr x1, =CPU_RELEASE_ADDR 196 ldr x0, [x1] 197 cbz x0, slave_cpu 198 br x0 /* branch to the given address */ 199#endif /* CONFIG_ARMV8_MULTIENTRY */ 200master_cpu: 201 bl _main 202 203#ifdef CONFIG_SYS_RESET_SCTRL 204reset_sctrl: 205 switch_el x1, 3f, 2f, 1f 2063: 207 mrs x0, sctlr_el3 208 b 0f 2092: 210 mrs x0, sctlr_el2 211 b 0f 2121: 213 mrs x0, sctlr_el1 214 2150: 216 ldr x1, =0xfdfffffa 217 and x0, x0, x1 218 219 switch_el x1, 6f, 5f, 4f 2206: 221 msr sctlr_el3, x0 222 b 7f 2235: 224 msr sctlr_el2, x0 225 b 7f 2264: 227 msr sctlr_el1, x0 228 2297: 230 dsb sy 231 isb 232 b __asm_invalidate_tlb_all 233 ret 234#endif 235 236/*-----------------------------------------------------------------------*/ 237 238WEAK(apply_core_errata) 239 240 mov x29, lr /* Save LR */ 241 /* For now, we support Cortex-A57 specific errata only */ 242 243 /* Check if we are running on a Cortex-A57 core */ 244 branch_if_a57_core x0, apply_a57_core_errata 2450: 246 mov lr, x29 /* Restore LR */ 247 ret 248 249apply_a57_core_errata: 250 251#ifdef CONFIG_ARM_ERRATA_828024 252 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ 253 /* Disable non-allocate hint of w-b-n-a memory type */ 254 orr x0, x0, #1 << 49 255 /* Disable write streaming no L1-allocate threshold */ 256 orr x0, x0, #3 << 25 257 /* Disable write streaming no-allocate threshold */ 258 orr x0, x0, #3 << 27 259 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ 260#endif 261 262#ifdef CONFIG_ARM_ERRATA_826974 263 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ 264 /* Disable speculative load execution ahead of a DMB */ 265 orr x0, x0, #1 << 59 266 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ 267#endif 268 269#ifdef CONFIG_ARM_ERRATA_833471 270 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ 271 /* FPSCR write flush. 272 * Note that in some cases where a flush is unnecessary this 273 could impact performance. */ 274 orr x0, x0, #1 << 38 275 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ 276#endif 277 278#ifdef CONFIG_ARM_ERRATA_829520 279 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ 280 /* Disable Indirect Predictor bit will prevent this erratum 281 from occurring 282 * Note that in some cases where a flush is unnecessary this 283 could impact performance. */ 284 orr x0, x0, #1 << 4 285 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ 286#endif 287 288#ifdef CONFIG_ARM_ERRATA_833069 289 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ 290 /* Disable Enable Invalidates of BTB bit */ 291 and x0, x0, #0xE 292 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ 293#endif 294 b 0b 295ENDPROC(apply_core_errata) 296 297/*-----------------------------------------------------------------------*/ 298 299WEAK(lowlevel_init) 300 mov x29, lr /* Save LR */ 301 302#if CONFIG_IS_ENABLED(IRQ) 303 branch_if_slave x0, 1f 304 ldr x0, =GICD_BASE 305 bl gic_init_secure 3061: 307#if defined(CONFIG_GICV3) 308 ldr x0, =GICR_BASE 309 bl gic_init_secure_percpu 310#elif defined(CONFIG_GICV2) 311 ldr x0, =GICD_BASE 312 ldr x1, =GICC_BASE 313 bl gic_init_secure_percpu 314#endif 315#endif 316 317#ifdef CONFIG_ARMV8_MULTIENTRY 318 branch_if_master x0, x1, 2f 319 320 /* 321 * Slave should wait for master clearing spin table. 322 * This sync prevent salves observing incorrect 323 * value of spin table and jumping to wrong place. 324 */ 325#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) 326#ifdef CONFIG_GICV2 327 ldr x0, =GICC_BASE 328#endif 329 bl gic_wait_for_interrupt 330#endif 331 332 /* 333 * All slaves will enter EL2 and optionally EL1. 334 */ 335 adr x4, lowlevel_in_el2 336 ldr x5, =ES_TO_AARCH64 337 bl armv8_switch_to_el2 338 339lowlevel_in_el2: 340#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 341 adr x4, lowlevel_in_el1 342 ldr x5, =ES_TO_AARCH64 343 bl armv8_switch_to_el1 344 345lowlevel_in_el1: 346#endif 347 348#endif /* CONFIG_ARMV8_MULTIENTRY */ 349 3502: 351 mov lr, x29 /* Restore LR */ 352 ret 353ENDPROC(lowlevel_init) 354 355WEAK(smp_kick_all_cpus) 356 /* Kick secondary cpus up by SGI 0 interrupt */ 357#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) 358 ldr x0, =GICD_BASE 359 b gic_kick_secondary_cpus 360#endif 361 ret 362ENDPROC(smp_kick_all_cpus) 363 364/*-----------------------------------------------------------------------*/ 365 366ENTRY(c_runtime_cpu_setup) 367 /* Relocate vBAR */ 368 adr x0, vectors 369 switch_el x1, 3f, 2f, 1f 3703: msr vbar_el3, x0 371 b 0f 3722: msr vbar_el2, x0 373 b 0f 3741: msr vbar_el1, x0 3750: 376 377 ret 378ENDPROC(c_runtime_cpu_setup) 379 380WEAK(save_boot_params) 381 b save_boot_params_ret /* back to my caller */ 382ENDPROC(save_boot_params) 383#endif 384