1/* 2 * (C) Copyright 2013 3 * David Feng <fenghua@phytium.com.cn> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8#include <asm-offsets.h> 9#include <config.h> 10#include <linux/linkage.h> 11#include <asm/macro.h> 12#include <asm/armv8/mmu.h> 13 14/************************************************************************* 15 * 16 * Startup Code (reset vector) 17 * 18 *************************************************************************/ 19 20.globl _start 21_start: 22#ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK 23/* 24 * Various SoCs need something special and SoC-specific up front in 25 * order to boot, allow them to set that in their boot0.h file and then 26 * use it here. 27 */ 28#include <asm/arch/boot0.h> 29#else 30 b reset 31#endif 32 33#if !CONFIG_IS_ENABLED(TINY_FRAMEWORK) 34 .align 3 35 36.globl _TEXT_BASE 37_TEXT_BASE: 38#if defined(CONFIG_SPL_BUILD) 39 .quad CONFIG_SPL_TEXT_BASE 40#else 41 .quad CONFIG_SYS_TEXT_BASE 42#endif 43 44/* 45 * These are defined in the linker script. 46 */ 47.globl _end_ofs 48_end_ofs: 49 .quad _end - _start 50 51.globl _bss_start_ofs 52_bss_start_ofs: 53 .quad __bss_start - _start 54 55.globl _bss_end_ofs 56_bss_end_ofs: 57 .quad __bss_end - _start 58 59reset: 60 /* Allow the board to save important registers */ 61 b save_boot_params 62.globl save_boot_params_ret 63save_boot_params_ret: 64 65#if CONFIG_POSITION_INDEPENDENT 66 /* 67 * Fix .rela.dyn relocations. This allows U-Boot to be loaded to and 68 * executed at a different address than it was linked at. 69 */ 70pie_fixup: 71 adr x0, _start /* x0 <- Runtime value of _start */ 72 ldr x1, _TEXT_BASE /* x1 <- Linked value of _start */ 73 sub x9, x0, x1 /* x9 <- Run-vs-link offset */ 74 adr x2, __rel_dyn_start /* x2 <- Runtime &__rel_dyn_start */ 75 adr x3, __rel_dyn_end /* x3 <- Runtime &__rel_dyn_end */ 76pie_fix_loop: 77 ldp x0, x1, [x2], #16 /* (x0, x1) <- (Link location, fixup) */ 78 ldr x4, [x2], #8 /* x4 <- addend */ 79 cmp w1, #1027 /* relative fixup? */ 80 bne pie_skip_reloc 81 /* relative fix: store addend plus offset at dest location */ 82 add x0, x0, x9 83 add x4, x4, x9 84 str x4, [x0] 85pie_skip_reloc: 86 cmp x2, x3 87 b.lo pie_fix_loop 88pie_fixup_done: 89#endif 90 91#ifdef CONFIG_SYS_RESET_SCTRL 92 bl reset_sctrl 93#endif 94 /* 95 * Could be EL3/EL2/EL1, Initial State: 96 * Little Endian, MMU Disabled, i/dCache Disabled 97 */ 98 adr x0, vectors 99 switch_el x1, 3f, 2f, 1f 1003: msr vbar_el3, x0 101 mrs x0, scr_el3 102 orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */ 103 msr scr_el3, x0 104 msr cptr_el3, xzr /* Enable FP/SIMD */ 105#ifdef COUNTER_FREQUENCY 106 ldr x0, =COUNTER_FREQUENCY 107 msr cntfrq_el0, x0 /* Initialize CNTFRQ */ 108#endif 109 b 0f 1102: msr vbar_el2, x0 111 mov x0, #0x33ff 112 msr cptr_el2, x0 /* Enable FP/SIMD */ 113 b 0f 1141: msr vbar_el1, x0 115 mov x0, #3 << 20 116 msr cpacr_el1, x0 /* Enable FP/SIMD */ 1170: 118 119 /* 120 * Enable SMPEN bit for coherency. 121 * This register is not architectural but at the moment 122 * this bit should be set for A53/A57/A72. 123 */ 124#ifdef CONFIG_ARMV8_SET_SMPEN 125 switch_el x1, 3f, 1f, 1f 1263: 127 mrs x0, S3_1_c15_c2_1 /* cpuectlr_el1 */ 128 orr x0, x0, #0x40 129 msr S3_1_c15_c2_1, x0 1301: 131#endif 132 133 /* Apply ARM core specific erratas */ 134 bl apply_core_errata 135 136 /* 137 * Cache/BPB/TLB Invalidate 138 * i-cache is invalidated before enabled in icache_enable() 139 * tlb is invalidated before mmu is enabled in dcache_enable() 140 * d-cache is invalidated before enabled in dcache_enable() 141 */ 142 143 /* Processor specific initialization */ 144 bl lowlevel_init 145 146#if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD) 147 branch_if_master x0, x1, master_cpu 148 b spin_table_secondary_jump 149 /* never return */ 150#elif defined(CONFIG_ARMV8_MULTIENTRY) 151 branch_if_master x0, x1, master_cpu 152 153 /* 154 * Slave CPUs 155 */ 156slave_cpu: 157 wfe 158 ldr x1, =CPU_RELEASE_ADDR 159 ldr x0, [x1] 160 cbz x0, slave_cpu 161 br x0 /* branch to the given address */ 162#endif /* CONFIG_ARMV8_MULTIENTRY */ 163master_cpu: 164 bl _main 165 166#ifdef CONFIG_SYS_RESET_SCTRL 167reset_sctrl: 168 switch_el x1, 3f, 2f, 1f 1693: 170 mrs x0, sctlr_el3 171 b 0f 1722: 173 mrs x0, sctlr_el2 174 b 0f 1751: 176 mrs x0, sctlr_el1 177 1780: 179 ldr x1, =0xfdfffffa 180 and x0, x0, x1 181 182 switch_el x1, 6f, 5f, 4f 1836: 184 msr sctlr_el3, x0 185 b 7f 1865: 187 msr sctlr_el2, x0 188 b 7f 1894: 190 msr sctlr_el1, x0 191 1927: 193 dsb sy 194 isb 195 b __asm_invalidate_tlb_all 196 ret 197#endif 198 199/*-----------------------------------------------------------------------*/ 200 201WEAK(apply_core_errata) 202 203 mov x29, lr /* Save LR */ 204 /* For now, we support Cortex-A57 specific errata only */ 205 206 /* Check if we are running on a Cortex-A57 core */ 207 branch_if_a57_core x0, apply_a57_core_errata 2080: 209 mov lr, x29 /* Restore LR */ 210 ret 211 212apply_a57_core_errata: 213 214#ifdef CONFIG_ARM_ERRATA_828024 215 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ 216 /* Disable non-allocate hint of w-b-n-a memory type */ 217 orr x0, x0, #1 << 49 218 /* Disable write streaming no L1-allocate threshold */ 219 orr x0, x0, #3 << 25 220 /* Disable write streaming no-allocate threshold */ 221 orr x0, x0, #3 << 27 222 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ 223#endif 224 225#ifdef CONFIG_ARM_ERRATA_826974 226 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ 227 /* Disable speculative load execution ahead of a DMB */ 228 orr x0, x0, #1 << 59 229 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ 230#endif 231 232#ifdef CONFIG_ARM_ERRATA_833471 233 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ 234 /* FPSCR write flush. 235 * Note that in some cases where a flush is unnecessary this 236 could impact performance. */ 237 orr x0, x0, #1 << 38 238 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ 239#endif 240 241#ifdef CONFIG_ARM_ERRATA_829520 242 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ 243 /* Disable Indirect Predictor bit will prevent this erratum 244 from occurring 245 * Note that in some cases where a flush is unnecessary this 246 could impact performance. */ 247 orr x0, x0, #1 << 4 248 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ 249#endif 250 251#ifdef CONFIG_ARM_ERRATA_833069 252 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ 253 /* Disable Enable Invalidates of BTB bit */ 254 and x0, x0, #0xE 255 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ 256#endif 257 b 0b 258ENDPROC(apply_core_errata) 259 260/*-----------------------------------------------------------------------*/ 261 262WEAK(lowlevel_init) 263 mov x29, lr /* Save LR */ 264 265#if CONFIG_IS_ENABLED(IRQ) 266 branch_if_slave x0, 1f 267 ldr x0, =GICD_BASE 268 bl gic_init_secure 2691: 270#if defined(CONFIG_GICV3) 271 ldr x0, =GICR_BASE 272 bl gic_init_secure_percpu 273#elif defined(CONFIG_GICV2) 274 ldr x0, =GICD_BASE 275 ldr x1, =GICC_BASE 276 bl gic_init_secure_percpu 277#endif 278#endif 279 280#ifdef CONFIG_ARMV8_MULTIENTRY 281 branch_if_master x0, x1, 2f 282 283 /* 284 * Slave should wait for master clearing spin table. 285 * This sync prevent salves observing incorrect 286 * value of spin table and jumping to wrong place. 287 */ 288#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) 289#ifdef CONFIG_GICV2 290 ldr x0, =GICC_BASE 291#endif 292 bl gic_wait_for_interrupt 293#endif 294 295 /* 296 * All slaves will enter EL2 and optionally EL1. 297 */ 298 adr x4, lowlevel_in_el2 299 ldr x5, =ES_TO_AARCH64 300 bl armv8_switch_to_el2 301 302lowlevel_in_el2: 303#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 304 adr x4, lowlevel_in_el1 305 ldr x5, =ES_TO_AARCH64 306 bl armv8_switch_to_el1 307 308lowlevel_in_el1: 309#endif 310 311#endif /* CONFIG_ARMV8_MULTIENTRY */ 312 3132: 314 mov lr, x29 /* Restore LR */ 315 ret 316ENDPROC(lowlevel_init) 317 318WEAK(smp_kick_all_cpus) 319 /* Kick secondary cpus up by SGI 0 interrupt */ 320#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) 321 ldr x0, =GICD_BASE 322 b gic_kick_secondary_cpus 323#endif 324 ret 325ENDPROC(smp_kick_all_cpus) 326 327/*-----------------------------------------------------------------------*/ 328 329ENTRY(c_runtime_cpu_setup) 330 /* Relocate vBAR */ 331 adr x0, vectors 332 switch_el x1, 3f, 2f, 1f 3333: msr vbar_el3, x0 334 b 0f 3352: msr vbar_el2, x0 336 b 0f 3371: msr vbar_el1, x0 3380: 339 340 ret 341ENDPROC(c_runtime_cpu_setup) 342 343WEAK(save_boot_params) 344 b save_boot_params_ret /* back to my caller */ 345ENDPROC(save_boot_params) 346#endif 347