1 /* 2 * Copyright 2014-2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/system.h> 10 #include <asm/arch/mp.h> 11 #include <asm/arch/soc.h> 12 #include "cpu.h" 13 #include <asm/arch-fsl-layerscape/soc.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 void *get_spin_tbl_addr(void) 18 { 19 return &__spin_table; 20 } 21 22 phys_addr_t determine_mp_bootpg(void) 23 { 24 return (phys_addr_t)&secondary_boot_code; 25 } 26 27 #ifdef CONFIG_FSL_LSCH3 28 void wake_secondary_core_n(int cluster, int core, int cluster_cores) 29 { 30 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 31 struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR); 32 u32 mpidr = 0; 33 34 mpidr = ((cluster << 8) | core); 35 /* 36 * mpidr_el1 register value of core which needs to be released 37 * is written to scratchrw[6] register 38 */ 39 gur_out32(&gur->scratchrw[6], mpidr); 40 asm volatile("dsb st" : : : "memory"); 41 rst->brrl |= 1 << ((cluster * cluster_cores) + core); 42 asm volatile("dsb st" : : : "memory"); 43 /* 44 * scratchrw[6] register value is polled 45 * when the value becomes zero, this means that this core is up 46 * and running, next core can be released now 47 */ 48 while (gur_in32(&gur->scratchrw[6]) != 0) 49 ; 50 } 51 #endif 52 53 int fsl_layerscape_wake_seconday_cores(void) 54 { 55 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 56 #ifdef CONFIG_FSL_LSCH3 57 struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR); 58 u32 svr, ver, cluster, type; 59 int j = 0, cluster_cores = 0; 60 #elif defined(CONFIG_FSL_LSCH2) 61 struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR); 62 #endif 63 u32 cores, cpu_up_mask = 1; 64 int i, timeout = 10; 65 u64 *table = get_spin_tbl_addr(); 66 67 #ifdef COUNTER_FREQUENCY_REAL 68 /* update for secondary cores */ 69 __real_cntfrq = COUNTER_FREQUENCY_REAL; 70 flush_dcache_range((unsigned long)&__real_cntfrq, 71 (unsigned long)&__real_cntfrq + 8); 72 #endif 73 74 cores = cpu_mask(); 75 /* Clear spin table so that secondary processors 76 * observe the correct value after waking up from wfe. 77 */ 78 memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE); 79 flush_dcache_range((unsigned long)table, 80 (unsigned long)table + 81 (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE)); 82 83 printf("Waking secondary cores to start from %lx\n", gd->relocaddr); 84 85 #ifdef CONFIG_FSL_LSCH3 86 gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32)); 87 gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr); 88 89 svr = gur_in32(&gur->svr); 90 ver = SVR_SOC_VER(svr); 91 if (ver == SVR_LS2080A || ver == SVR_LS2085A) { 92 gur_out32(&gur->scratchrw[6], 1); 93 asm volatile("dsb st" : : : "memory"); 94 rst->brrl = cores; 95 asm volatile("dsb st" : : : "memory"); 96 } else { 97 /* 98 * Release the cores out of reset one-at-a-time to avoid 99 * power spikes 100 */ 101 i = 0; 102 cluster = in_le32(&gur->tp_cluster[i].lower); 103 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 104 type = initiator_type(cluster, j); 105 if (type && 106 TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM) 107 cluster_cores++; 108 } 109 110 do { 111 cluster = in_le32(&gur->tp_cluster[i].lower); 112 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 113 type = initiator_type(cluster, j); 114 if (type && 115 TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM) 116 wake_secondary_core_n(i, j, 117 cluster_cores); 118 } 119 i++; 120 } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); 121 } 122 #elif defined(CONFIG_FSL_LSCH2) 123 scfg_out32(&scfg->scratchrw[0], (u32)(gd->relocaddr >> 32)); 124 scfg_out32(&scfg->scratchrw[1], (u32)gd->relocaddr); 125 asm volatile("dsb st" : : : "memory"); 126 gur_out32(&gur->brrl, cores); 127 asm volatile("dsb st" : : : "memory"); 128 129 /* Bootup online cores */ 130 scfg_out32(&scfg->corebcr, cores); 131 #endif 132 /* This is needed as a precautionary measure. 133 * If some code before this has accidentally released the secondary 134 * cores then the pre-bootloader code will trap them in a "wfe" unless 135 * the scratchrw[6] is set. In this case we need a sev here to get these 136 * cores moving again. 137 */ 138 asm volatile("sev"); 139 140 while (timeout--) { 141 flush_dcache_range((unsigned long)table, (unsigned long)table + 142 CONFIG_MAX_CPUS * 64); 143 for (i = 1; i < CONFIG_MAX_CPUS; i++) { 144 if (table[i * WORDS_PER_SPIN_TABLE_ENTRY + 145 SPIN_TABLE_ELEM_STATUS_IDX]) 146 cpu_up_mask |= 1 << i; 147 } 148 if (hweight32(cpu_up_mask) == hweight32(cores)) 149 break; 150 udelay(10); 151 } 152 if (timeout <= 0) { 153 printf("Not all cores (0x%x) are up (0x%x)\n", 154 cores, cpu_up_mask); 155 return 1; 156 } 157 printf("All (%d) cores are up.\n", hweight32(cores)); 158 159 return 0; 160 } 161 162 int is_core_valid(unsigned int core) 163 { 164 return !!((1 << core) & cpu_mask()); 165 } 166 167 static int is_pos_valid(unsigned int pos) 168 { 169 return !!((1 << pos) & cpu_pos_mask()); 170 } 171 172 int is_core_online(u64 cpu_id) 173 { 174 u64 *table; 175 int pos = id_to_core(cpu_id); 176 table = (u64 *)get_spin_tbl_addr() + pos * WORDS_PER_SPIN_TABLE_ENTRY; 177 return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1; 178 } 179 180 int cpu_reset(int nr) 181 { 182 puts("Feature is not implemented.\n"); 183 184 return 0; 185 } 186 187 int cpu_disable(int nr) 188 { 189 puts("Feature is not implemented.\n"); 190 191 return 0; 192 } 193 194 static int core_to_pos(int nr) 195 { 196 u32 cores = cpu_pos_mask(); 197 int i, count = 0; 198 199 if (nr == 0) { 200 return 0; 201 } else if (nr >= hweight32(cores)) { 202 puts("Not a valid core number.\n"); 203 return -1; 204 } 205 206 for (i = 1; i < 32; i++) { 207 if (is_pos_valid(i)) { 208 count++; 209 if (count == nr) 210 break; 211 } 212 } 213 214 if (count != nr) 215 return -1; 216 217 return i; 218 } 219 220 int cpu_status(int nr) 221 { 222 u64 *table; 223 int pos; 224 225 if (nr == 0) { 226 table = (u64 *)get_spin_tbl_addr(); 227 printf("table base @ 0x%p\n", table); 228 } else { 229 pos = core_to_pos(nr); 230 if (pos < 0) 231 return -1; 232 table = (u64 *)get_spin_tbl_addr() + pos * 233 WORDS_PER_SPIN_TABLE_ENTRY; 234 printf("table @ 0x%p\n", table); 235 printf(" addr - 0x%016llx\n", 236 table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX]); 237 printf(" status - 0x%016llx\n", 238 table[SPIN_TABLE_ELEM_STATUS_IDX]); 239 printf(" lpid - 0x%016llx\n", 240 table[SPIN_TABLE_ELEM_LPID_IDX]); 241 } 242 243 return 0; 244 } 245 246 int cpu_release(int nr, int argc, char * const argv[]) 247 { 248 u64 boot_addr; 249 u64 *table = (u64 *)get_spin_tbl_addr(); 250 int pos; 251 252 pos = core_to_pos(nr); 253 if (pos <= 0) 254 return -1; 255 256 table += pos * WORDS_PER_SPIN_TABLE_ENTRY; 257 boot_addr = simple_strtoull(argv[0], NULL, 16); 258 table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr; 259 flush_dcache_range((unsigned long)table, 260 (unsigned long)table + SPIN_TABLE_ELEM_SIZE); 261 asm volatile("dsb st"); 262 smp_kick_all_cpus(); /* only those with entry addr set will run */ 263 /* 264 * When the first release command runs, all cores are set to go. Those 265 * without a valid entry address will be trapped by "wfe". "sev" kicks 266 * them off to check the address again. When set, they continue to run. 267 */ 268 asm volatile("sev"); 269 270 return 0; 271 } 272