1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 */ 19 20 #include <common.h> 21 #include <asm/io.h> 22 #include <asm/arch/imx-regs.h> 23 #include <asm/arch/clock.h> 24 #include <asm/arch/crm_regs.h> 25 #include <netdev.h> 26 #ifdef CONFIG_FSL_ESDHC 27 #include <fsl_esdhc.h> 28 #endif 29 30 #ifdef CONFIG_FSL_ESDHC 31 DECLARE_GLOBAL_DATA_PTR; 32 #endif 33 34 #ifdef CONFIG_MXC_OCOTP 35 void enable_ocotp_clk(unsigned char enable) 36 { 37 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; 38 u32 reg; 39 40 reg = readl(&ccm->ccgr6); 41 if (enable) 42 reg |= CCM_CCGR6_OCOTP_CTRL_MASK; 43 else 44 reg &= ~CCM_CCGR6_OCOTP_CTRL_MASK; 45 writel(reg, &ccm->ccgr6); 46 } 47 #endif 48 49 static u32 get_mcu_main_clk(void) 50 { 51 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; 52 u32 ccm_ccsr, ccm_cacrr, armclk_div; 53 u32 sysclk_sel, pll_pfd_sel = 0; 54 u32 freq = 0; 55 56 ccm_ccsr = readl(&ccm->ccsr); 57 sysclk_sel = ccm_ccsr & CCM_CCSR_SYS_CLK_SEL_MASK; 58 sysclk_sel >>= CCM_CCSR_SYS_CLK_SEL_OFFSET; 59 60 ccm_cacrr = readl(&ccm->cacrr); 61 armclk_div = ccm_cacrr & CCM_CACRR_ARM_CLK_DIV_MASK; 62 armclk_div >>= CCM_CACRR_ARM_CLK_DIV_OFFSET; 63 armclk_div += 1; 64 65 switch (sysclk_sel) { 66 case 0: 67 freq = FASE_CLK_FREQ; 68 break; 69 case 1: 70 freq = SLOW_CLK_FREQ; 71 break; 72 case 2: 73 pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL2_PFD_CLK_SEL_MASK; 74 pll_pfd_sel >>= CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET; 75 if (pll_pfd_sel == 0) 76 freq = PLL2_MAIN_FREQ; 77 else if (pll_pfd_sel == 1) 78 freq = PLL2_PFD1_FREQ; 79 else if (pll_pfd_sel == 2) 80 freq = PLL2_PFD2_FREQ; 81 else if (pll_pfd_sel == 3) 82 freq = PLL2_PFD3_FREQ; 83 else if (pll_pfd_sel == 4) 84 freq = PLL2_PFD4_FREQ; 85 break; 86 case 3: 87 freq = PLL2_MAIN_FREQ; 88 break; 89 case 4: 90 pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL1_PFD_CLK_SEL_MASK; 91 pll_pfd_sel >>= CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET; 92 if (pll_pfd_sel == 0) 93 freq = PLL1_MAIN_FREQ; 94 else if (pll_pfd_sel == 1) 95 freq = PLL1_PFD1_FREQ; 96 else if (pll_pfd_sel == 2) 97 freq = PLL1_PFD2_FREQ; 98 else if (pll_pfd_sel == 3) 99 freq = PLL1_PFD3_FREQ; 100 else if (pll_pfd_sel == 4) 101 freq = PLL1_PFD4_FREQ; 102 break; 103 case 5: 104 freq = PLL3_MAIN_FREQ; 105 break; 106 default: 107 printf("unsupported system clock select\n"); 108 } 109 110 return freq / armclk_div; 111 } 112 113 static u32 get_bus_clk(void) 114 { 115 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; 116 u32 ccm_cacrr, busclk_div; 117 118 ccm_cacrr = readl(&ccm->cacrr); 119 120 busclk_div = ccm_cacrr & CCM_CACRR_BUS_CLK_DIV_MASK; 121 busclk_div >>= CCM_CACRR_BUS_CLK_DIV_OFFSET; 122 busclk_div += 1; 123 124 return get_mcu_main_clk() / busclk_div; 125 } 126 127 static u32 get_ipg_clk(void) 128 { 129 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; 130 u32 ccm_cacrr, ipgclk_div; 131 132 ccm_cacrr = readl(&ccm->cacrr); 133 134 ipgclk_div = ccm_cacrr & CCM_CACRR_IPG_CLK_DIV_MASK; 135 ipgclk_div >>= CCM_CACRR_IPG_CLK_DIV_OFFSET; 136 ipgclk_div += 1; 137 138 return get_bus_clk() / ipgclk_div; 139 } 140 141 static u32 get_uart_clk(void) 142 { 143 return get_ipg_clk(); 144 } 145 146 static u32 get_sdhc_clk(void) 147 { 148 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; 149 u32 ccm_cscmr1, ccm_cscdr2, sdhc_clk_sel, sdhc_clk_div; 150 u32 freq = 0; 151 152 ccm_cscmr1 = readl(&ccm->cscmr1); 153 sdhc_clk_sel = ccm_cscmr1 & CCM_CSCMR1_ESDHC1_CLK_SEL_MASK; 154 sdhc_clk_sel >>= CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET; 155 156 ccm_cscdr2 = readl(&ccm->cscdr2); 157 sdhc_clk_div = ccm_cscdr2 & CCM_CSCDR2_ESDHC1_CLK_DIV_MASK; 158 sdhc_clk_div >>= CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET; 159 sdhc_clk_div += 1; 160 161 switch (sdhc_clk_sel) { 162 case 0: 163 freq = PLL3_MAIN_FREQ; 164 break; 165 case 1: 166 freq = PLL3_PFD3_FREQ; 167 break; 168 case 2: 169 freq = PLL1_PFD3_FREQ; 170 break; 171 case 3: 172 freq = get_bus_clk(); 173 break; 174 } 175 176 return freq / sdhc_clk_div; 177 } 178 179 u32 get_fec_clk(void) 180 { 181 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; 182 u32 ccm_cscmr2, rmii_clk_sel; 183 u32 freq = 0; 184 185 ccm_cscmr2 = readl(&ccm->cscmr2); 186 rmii_clk_sel = ccm_cscmr2 & CCM_CSCMR2_RMII_CLK_SEL_MASK; 187 rmii_clk_sel >>= CCM_CSCMR2_RMII_CLK_SEL_OFFSET; 188 189 switch (rmii_clk_sel) { 190 case 0: 191 freq = ENET_EXTERNAL_CLK; 192 break; 193 case 1: 194 freq = AUDIO_EXTERNAL_CLK; 195 break; 196 case 2: 197 freq = PLL5_MAIN_FREQ; 198 break; 199 case 3: 200 freq = PLL5_MAIN_FREQ / 2; 201 break; 202 } 203 204 return freq; 205 } 206 207 static u32 get_i2c_clk(void) 208 { 209 return get_ipg_clk(); 210 } 211 212 unsigned int mxc_get_clock(enum mxc_clock clk) 213 { 214 switch (clk) { 215 case MXC_ARM_CLK: 216 return get_mcu_main_clk(); 217 case MXC_BUS_CLK: 218 return get_bus_clk(); 219 case MXC_IPG_CLK: 220 return get_ipg_clk(); 221 case MXC_UART_CLK: 222 return get_uart_clk(); 223 case MXC_ESDHC_CLK: 224 return get_sdhc_clk(); 225 case MXC_FEC_CLK: 226 return get_fec_clk(); 227 case MXC_I2C_CLK: 228 return get_i2c_clk(); 229 default: 230 break; 231 } 232 return -1; 233 } 234 235 /* Dump some core clocks */ 236 int do_vf610_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, 237 char * const argv[]) 238 { 239 printf("\n"); 240 printf("cpu clock : %8d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000); 241 printf("bus clock : %8d MHz\n", mxc_get_clock(MXC_BUS_CLK) / 1000000); 242 printf("ipg clock : %8d MHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000000); 243 244 return 0; 245 } 246 247 U_BOOT_CMD( 248 clocks, CONFIG_SYS_MAXARGS, 1, do_vf610_showclocks, 249 "display clocks", 250 "" 251 ); 252 253 #ifdef CONFIG_FEC_MXC 254 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) 255 { 256 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 257 struct fuse_bank *bank = &ocotp->bank[4]; 258 struct fuse_bank4_regs *fuse = 259 (struct fuse_bank4_regs *)bank->fuse_regs; 260 261 u32 value = readl(&fuse->mac_addr0); 262 mac[0] = (value >> 8); 263 mac[1] = value; 264 265 value = readl(&fuse->mac_addr1); 266 mac[2] = value >> 24; 267 mac[3] = value >> 16; 268 mac[4] = value >> 8; 269 mac[5] = value; 270 } 271 #endif 272 273 #if defined(CONFIG_DISPLAY_CPUINFO) 274 static char *get_reset_cause(void) 275 { 276 u32 cause; 277 struct src *src_regs = (struct src *)SRC_BASE_ADDR; 278 279 cause = readl(&src_regs->srsr); 280 writel(cause, &src_regs->srsr); 281 cause &= 0xff; 282 283 switch (cause) { 284 case 0x08: 285 return "WDOG"; 286 case 0x20: 287 return "JTAG HIGH-Z"; 288 case 0x80: 289 return "EXTERNAL RESET"; 290 case 0xfd: 291 return "POR"; 292 default: 293 return "unknown reset"; 294 } 295 } 296 297 int print_cpuinfo(void) 298 { 299 printf("CPU: Freescale Vybrid VF610 at %d MHz\n", 300 mxc_get_clock(MXC_ARM_CLK) / 1000000); 301 printf("Reset cause: %s\n", get_reset_cause()); 302 303 return 0; 304 } 305 #endif 306 307 int cpu_eth_init(bd_t *bis) 308 { 309 int rc = -ENODEV; 310 311 #if defined(CONFIG_FEC_MXC) 312 rc = fecmxc_initialize(bis); 313 #endif 314 315 return rc; 316 } 317 318 #ifdef CONFIG_FSL_ESDHC 319 int cpu_mmc_init(bd_t *bis) 320 { 321 return fsl_esdhc_mmc_init(bis); 322 } 323 #endif 324 325 int get_clocks(void) 326 { 327 #ifdef CONFIG_FSL_ESDHC 328 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 329 #endif 330 return 0; 331 } 332