1/* 2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com> 12 * 13 * See file CREDITS for list of people who contributed to this 14 * project. 15 * 16 * This program is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation; either version 2 of 19 * the License, or (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 29 * MA 02111-1307 USA 30 */ 31 32#include <asm-offsets.h> 33#include <config.h> 34#include <version.h> 35#include <asm/system.h> 36#include <linux/linkage.h> 37 38.globl _start 39_start: b reset 40 ldr pc, _undefined_instruction 41 ldr pc, _software_interrupt 42 ldr pc, _prefetch_abort 43 ldr pc, _data_abort 44 ldr pc, _not_used 45 ldr pc, _irq 46 ldr pc, _fiq 47#ifdef CONFIG_SPL_BUILD 48_undefined_instruction: .word _undefined_instruction 49_software_interrupt: .word _software_interrupt 50_prefetch_abort: .word _prefetch_abort 51_data_abort: .word _data_abort 52_not_used: .word _not_used 53_irq: .word _irq 54_fiq: .word _fiq 55_pad: .word 0x12345678 /* now 16*4=64 */ 56#else 57_undefined_instruction: .word undefined_instruction 58_software_interrupt: .word software_interrupt 59_prefetch_abort: .word prefetch_abort 60_data_abort: .word data_abort 61_not_used: .word not_used 62_irq: .word irq 63_fiq: .word fiq 64_pad: .word 0x12345678 /* now 16*4=64 */ 65#endif /* CONFIG_SPL_BUILD */ 66 67.global _end_vect 68_end_vect: 69 70 .balignl 16,0xdeadbeef 71/************************************************************************* 72 * 73 * Startup Code (reset vector) 74 * 75 * do important init only if we don't start from memory! 76 * setup Memory and board specific bits prior to relocation. 77 * relocate armboot to ram 78 * setup stack 79 * 80 *************************************************************************/ 81 82.globl _TEXT_BASE 83_TEXT_BASE: 84#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) 85 .word CONFIG_SPL_TEXT_BASE 86#else 87 .word CONFIG_SYS_TEXT_BASE 88#endif 89 90/* 91 * These are defined in the board-specific linker script. 92 */ 93.globl _bss_start_ofs 94_bss_start_ofs: 95 .word __bss_start - _start 96 97.globl _bss_end_ofs 98_bss_end_ofs: 99 .word __bss_end - _start 100 101.globl _end_ofs 102_end_ofs: 103 .word _end - _start 104 105#ifdef CONFIG_USE_IRQ 106/* IRQ stack memory (calculated at run-time) */ 107.globl IRQ_STACK_START 108IRQ_STACK_START: 109 .word 0x0badc0de 110 111/* IRQ stack memory (calculated at run-time) */ 112.globl FIQ_STACK_START 113FIQ_STACK_START: 114 .word 0x0badc0de 115#endif 116 117/* IRQ stack memory (calculated at run-time) + 8 bytes */ 118.globl IRQ_STACK_START_IN 119IRQ_STACK_START_IN: 120 .word 0x0badc0de 121 122/* 123 * the actual reset code 124 */ 125 126reset: 127 bl save_boot_params 128 /* 129 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode, 130 * except if in HYP mode already 131 */ 132 mrs r0, cpsr 133 and r1, r0, #0x1f @ mask mode bits 134 teq r1, #0x1a @ test for HYP mode 135 bicne r0, r0, #0x1f @ clear all mode bits 136 orrne r0, r0, #0x13 @ set SVC mode 137 orr r0, r0, #0xc0 @ disable FIQ and IRQ 138 msr cpsr,r0 139 140/* 141 * Setup vector: 142 * (OMAP4 spl TEXT_BASE is not 32 byte aligned. 143 * Continue to use ROM code vector only in OMAP4 spl) 144 */ 145#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) 146 /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */ 147 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register 148 bic r0, #CR_V @ V = 0 149 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register 150 151 /* Set vector address in CP15 VBAR register */ 152 ldr r0, =_start 153 mcr p15, 0, r0, c12, c0, 0 @Set VBAR 154#endif 155 156 /* the mask ROM code should have PLL and others stable */ 157#ifndef CONFIG_SKIP_LOWLEVEL_INIT 158 bl cpu_init_cp15 159 bl cpu_init_crit 160#endif 161 162 bl _main 163 164/*------------------------------------------------------------------------------*/ 165 166#ifndef CONFIG_SPL_BUILD 167/* 168 * void relocate_code(addr_moni) 169 * 170 * This function relocates the monitor code. 171 */ 172ENTRY(relocate_code) 173 mov r6, r0 /* save addr of destination */ 174 175 adr r0, _start 176 subs r9, r6, r0 /* r9 <- relocation offset */ 177 beq relocate_done /* skip relocation */ 178 mov r1, r6 /* r1 <- scratch for copy_loop */ 179 ldr r3, _image_copy_end_ofs 180 add r2, r0, r3 /* r2 <- source end address */ 181 182copy_loop: 183 ldmia r0!, {r10-r11} /* copy from source address [r0] */ 184 stmia r1!, {r10-r11} /* copy to target address [r1] */ 185 cmp r0, r2 /* until source end address [r2] */ 186 blo copy_loop 187 188 /* 189 * fix .rel.dyn relocations 190 */ 191 ldr r0, _TEXT_BASE /* r0 <- Text base */ 192 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 193 add r10, r10, r0 /* r10 <- sym table in FLASH */ 194 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 195 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 196 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 197 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 198fixloop: 199 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 200 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 201 ldr r1, [r2, #4] 202 and r7, r1, #0xff 203 cmp r7, #23 /* relative fixup? */ 204 beq fixrel 205 cmp r7, #2 /* absolute fixup? */ 206 beq fixabs 207 /* ignore unknown type of fixup */ 208 b fixnext 209fixabs: 210 /* absolute fix: set location to (offset) symbol value */ 211 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 212 add r1, r10, r1 /* r1 <- address of symbol in table */ 213 ldr r1, [r1, #4] /* r1 <- symbol value */ 214 add r1, r1, r9 /* r1 <- relocated sym addr */ 215 b fixnext 216fixrel: 217 /* relative fix: increase location by offset */ 218 ldr r1, [r0] 219 add r1, r1, r9 220fixnext: 221 str r1, [r0] 222 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 223 cmp r2, r3 224 blo fixloop 225 226relocate_done: 227 228 bx lr 229 230_image_copy_end_ofs: 231 .word __image_copy_end - _start 232_rel_dyn_start_ofs: 233 .word __rel_dyn_start - _start 234_rel_dyn_end_ofs: 235 .word __rel_dyn_end - _start 236_dynsym_start_ofs: 237 .word __dynsym_start - _start 238ENDPROC(relocate_code) 239 240#endif 241 242ENTRY(c_runtime_cpu_setup) 243/* 244 * If I-cache is enabled invalidate it 245 */ 246#ifndef CONFIG_SYS_ICACHE_OFF 247 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 248 mcr p15, 0, r0, c7, c10, 4 @ DSB 249 mcr p15, 0, r0, c7, c5, 4 @ ISB 250#endif 251/* 252 * Move vector table 253 */ 254 /* Set vector address in CP15 VBAR register */ 255 ldr r0, =_start 256 mcr p15, 0, r0, c12, c0, 0 @Set VBAR 257 258 bx lr 259 260ENDPROC(c_runtime_cpu_setup) 261 262/************************************************************************* 263 * 264 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) 265 * __attribute__((weak)); 266 * 267 * Stack pointer is not yet initialized at this moment 268 * Don't save anything to stack even if compiled with -O0 269 * 270 *************************************************************************/ 271ENTRY(save_boot_params) 272 bx lr @ back to my caller 273ENDPROC(save_boot_params) 274 .weak save_boot_params 275 276/************************************************************************* 277 * 278 * cpu_init_cp15 279 * 280 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless 281 * CONFIG_SYS_ICACHE_OFF is defined. 282 * 283 *************************************************************************/ 284ENTRY(cpu_init_cp15) 285 /* 286 * Invalidate L1 I/D 287 */ 288 mov r0, #0 @ set up for MCR 289 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs 290 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 291 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array 292 mcr p15, 0, r0, c7, c10, 4 @ DSB 293 mcr p15, 0, r0, c7, c5, 4 @ ISB 294 295 /* 296 * disable MMU stuff and caches 297 */ 298 mrc p15, 0, r0, c1, c0, 0 299 bic r0, r0, #0x00002000 @ clear bits 13 (--V-) 300 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) 301 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align 302 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB 303#ifdef CONFIG_SYS_ICACHE_OFF 304 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache 305#else 306 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache 307#endif 308 mcr p15, 0, r0, c1, c0, 0 309 310#ifdef CONFIG_ARM_ERRATA_716044 311 mrc p15, 0, r0, c1, c0, 0 @ read system control register 312 orr r0, r0, #1 << 11 @ set bit #11 313 mcr p15, 0, r0, c1, c0, 0 @ write system control register 314#endif 315 316#ifdef CONFIG_ARM_ERRATA_742230 317 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 318 orr r0, r0, #1 << 4 @ set bit #4 319 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 320#endif 321 322#ifdef CONFIG_ARM_ERRATA_743622 323 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 324 orr r0, r0, #1 << 6 @ set bit #6 325 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 326#endif 327 328#ifdef CONFIG_ARM_ERRATA_751472 329 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 330 orr r0, r0, #1 << 11 @ set bit #11 331 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 332#endif 333 334 mov pc, lr @ back to my caller 335ENDPROC(cpu_init_cp15) 336 337#ifndef CONFIG_SKIP_LOWLEVEL_INIT 338/************************************************************************* 339 * 340 * CPU_init_critical registers 341 * 342 * setup important registers 343 * setup memory timing 344 * 345 *************************************************************************/ 346ENTRY(cpu_init_crit) 347 /* 348 * Jump to board specific initialization... 349 * The Mask ROM will have already initialized 350 * basic memory. Go here to bump up clock rate and handle 351 * wake up conditions. 352 */ 353 b lowlevel_init @ go setup pll,mux,memory 354ENDPROC(cpu_init_crit) 355#endif 356 357#ifndef CONFIG_SPL_BUILD 358/* 359 ************************************************************************* 360 * 361 * Interrupt handling 362 * 363 ************************************************************************* 364 */ 365@ 366@ IRQ stack frame. 367@ 368#define S_FRAME_SIZE 72 369 370#define S_OLD_R0 68 371#define S_PSR 64 372#define S_PC 60 373#define S_LR 56 374#define S_SP 52 375 376#define S_IP 48 377#define S_FP 44 378#define S_R10 40 379#define S_R9 36 380#define S_R8 32 381#define S_R7 28 382#define S_R6 24 383#define S_R5 20 384#define S_R4 16 385#define S_R3 12 386#define S_R2 8 387#define S_R1 4 388#define S_R0 0 389 390#define MODE_SVC 0x13 391#define I_BIT 0x80 392 393/* 394 * use bad_save_user_regs for abort/prefetch/undef/swi ... 395 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 396 */ 397 398 .macro bad_save_user_regs 399 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current 400 @ user stack 401 stmia sp, {r0 - r12} @ Save user registers (now in 402 @ svc mode) r0-r12 403 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort 404 @ stack 405 ldmia r2, {r2 - r3} @ get values for "aborted" pc 406 @ and cpsr (into parm regs) 407 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 408 409 add r5, sp, #S_SP 410 mov r1, lr 411 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 412 mov r0, sp @ save current stack into r0 413 @ (param register) 414 .endm 415 416 .macro irq_save_user_regs 417 sub sp, sp, #S_FRAME_SIZE 418 stmia sp, {r0 - r12} @ Calling r0-r12 419 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !! 420 @ a reserved stack spot would 421 @ be good. 422 stmdb r8, {sp, lr}^ @ Calling SP, LR 423 str lr, [r8, #0] @ Save calling PC 424 mrs r6, spsr 425 str r6, [r8, #4] @ Save CPSR 426 str r0, [r8, #8] @ Save OLD_R0 427 mov r0, sp 428 .endm 429 430 .macro irq_restore_user_regs 431 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 432 mov r0, r0 433 ldr lr, [sp, #S_PC] @ Get PC 434 add sp, sp, #S_FRAME_SIZE 435 subs pc, lr, #4 @ return & move spsr_svc into 436 @ cpsr 437 .endm 438 439 .macro get_bad_stack 440 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter 441 @ in banked mode) 442 443 str lr, [r13] @ save caller lr in position 0 444 @ of saved stack 445 mrs lr, spsr @ get the spsr 446 str lr, [r13, #4] @ save spsr in position 1 of 447 @ saved stack 448 449 mov r13, #MODE_SVC @ prepare SVC-Mode 450 @ msr spsr_c, r13 451 msr spsr, r13 @ switch modes, make sure 452 @ moves will execute 453 mov lr, pc @ capture return pc 454 movs pc, lr @ jump to next instruction & 455 @ switch modes. 456 .endm 457 458 .macro get_bad_stack_swi 459 sub r13, r13, #4 @ space on current stack for 460 @ scratch reg. 461 str r0, [r13] @ save R0's value. 462 ldr r0, IRQ_STACK_START_IN @ get data regions start 463 @ spots for abort stack 464 str lr, [r0] @ save caller lr in position 0 465 @ of saved stack 466 mrs lr, spsr @ get the spsr 467 str lr, [r0, #4] @ save spsr in position 1 of 468 @ saved stack 469 ldr lr, [r0] @ restore lr 470 ldr r0, [r13] @ restore r0 471 add r13, r13, #4 @ pop stack entry 472 .endm 473 474 .macro get_irq_stack @ setup IRQ stack 475 ldr sp, IRQ_STACK_START 476 .endm 477 478 .macro get_fiq_stack @ setup FIQ stack 479 ldr sp, FIQ_STACK_START 480 .endm 481 482/* 483 * exception handlers 484 */ 485 .align 5 486undefined_instruction: 487 get_bad_stack 488 bad_save_user_regs 489 bl do_undefined_instruction 490 491 .align 5 492software_interrupt: 493 get_bad_stack_swi 494 bad_save_user_regs 495 bl do_software_interrupt 496 497 .align 5 498prefetch_abort: 499 get_bad_stack 500 bad_save_user_regs 501 bl do_prefetch_abort 502 503 .align 5 504data_abort: 505 get_bad_stack 506 bad_save_user_regs 507 bl do_data_abort 508 509 .align 5 510not_used: 511 get_bad_stack 512 bad_save_user_regs 513 bl do_not_used 514 515#ifdef CONFIG_USE_IRQ 516 517 .align 5 518irq: 519 get_irq_stack 520 irq_save_user_regs 521 bl do_irq 522 irq_restore_user_regs 523 524 .align 5 525fiq: 526 get_fiq_stack 527 /* someone ought to write a more effective fiq_save_user_regs */ 528 irq_save_user_regs 529 bl do_fiq 530 irq_restore_user_regs 531 532#else 533 534 .align 5 535irq: 536 get_bad_stack 537 bad_save_user_regs 538 bl do_irq 539 540 .align 5 541fiq: 542 get_bad_stack 543 bad_save_user_regs 544 bl do_fiq 545 546#endif /* CONFIG_USE_IRQ */ 547#endif /* CONFIG_SPL_BUILD */ 548