1/* 2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com> 12 * 13 * SPDX-License-Identifier: GPL-2.0+ 14 */ 15 16#include <asm-offsets.h> 17#include <config.h> 18#include <asm/system.h> 19#include <linux/linkage.h> 20#include <asm/armv7.h> 21 22/************************************************************************* 23 * 24 * Startup Code (reset vector) 25 * 26 * Do important init only if we don't start from memory! 27 * Setup memory and board specific bits prior to relocation. 28 * Relocate armboot to ram. Setup stack. 29 * 30 *************************************************************************/ 31 32 .globl reset 33 .globl save_boot_params_ret 34 .type save_boot_params_ret,%function 35#ifdef CONFIG_ARMV7_LPAE 36 .global switch_to_hypervisor_ret 37#endif 38 39#if !CONFIG_IS_ENABLED(TINY_FRAMEWORK) 40 41reset: 42 /* Allow the board to save important registers */ 43 b save_boot_params 44save_boot_params_ret: 45#ifdef CONFIG_ARMV7_LPAE 46/* 47 * check for Hypervisor support 48 */ 49 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 50 and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits 51 cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT) 52 beq switch_to_hypervisor 53switch_to_hypervisor_ret: 54#endif 55 /* 56 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode, 57 * except if in HYP mode already 58 */ 59 mrs r0, cpsr 60 and r1, r0, #0x1f @ mask mode bits 61 teq r1, #0x1a @ test for HYP mode 62 bicne r0, r0, #0x1f @ clear all mode bits 63 orrne r0, r0, #0x13 @ set SVC mode 64 orr r0, r0, #0xc0 @ disable FIQ and IRQ 65 msr cpsr,r0 66 67 /* Enable ACTLR.SMP bit */ 68 mrc p15, 0, r0, c1, c0, 1 69 orr r0, r0, #(1 << 6) @ Enable ACTLR.SMP bit 70 mcr p15, 0, r0, c1, c0, 1 71 72/* 73 * Setup vector: 74 * (OMAP4 spl TEXT_BASE is not 32 byte aligned. 75 * Continue to use ROM code vector only in OMAP4 spl) 76 */ 77#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) 78 /* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */ 79 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register 80 bic r0, #CR_V @ V = 0 81 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register 82 83 /* Set vector address in CP15 VBAR register */ 84 ldr r0, =_start 85 mcr p15, 0, r0, c12, c0, 0 @Set VBAR 86#endif 87 88 /* the mask ROM code should have PLL and others stable */ 89#ifndef CONFIG_SKIP_LOWLEVEL_INIT 90 bl cpu_init_cp15 91#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY 92 bl cpu_init_crit 93#endif 94#endif 95 96 bl _main 97 98/*------------------------------------------------------------------------------*/ 99 100ENTRY(c_runtime_cpu_setup) 101/* 102 * If I-cache is enabled invalidate it 103 */ 104#ifndef CONFIG_SYS_ICACHE_OFF 105 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 106 mcr p15, 0, r0, c7, c10, 4 @ DSB 107 mcr p15, 0, r0, c7, c5, 4 @ ISB 108#endif 109 110 bx lr 111 112ENDPROC(c_runtime_cpu_setup) 113 114#endif/* !CONFIG_IS_ENABLED(TINY_FRAMEWORK) */ 115 116/************************************************************************* 117 * 118 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) 119 * __attribute__((weak)); 120 * 121 * Stack pointer is not yet initialized at this moment 122 * Don't save anything to stack even if compiled with -O0 123 * 124 *************************************************************************/ 125ENTRY(save_boot_params) 126 b save_boot_params_ret @ back to my caller 127ENDPROC(save_boot_params) 128 .weak save_boot_params 129 130#ifdef CONFIG_ARMV7_LPAE 131ENTRY(switch_to_hypervisor) 132 b switch_to_hypervisor_ret 133ENDPROC(switch_to_hypervisor) 134 .weak switch_to_hypervisor 135#endif 136 137/************************************************************************* 138 * 139 * cpu_init_cp15 140 * 141 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless 142 * CONFIG_SYS_ICACHE_OFF is defined. 143 * 144 *************************************************************************/ 145ENTRY(cpu_init_cp15) 146 /* 147 * Invalidate L1 I/D 148 */ 149 mov r0, #0 @ set up for MCR 150 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs 151 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 152 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array 153 mcr p15, 0, r0, c7, c10, 4 @ DSB 154 mcr p15, 0, r0, c7, c5, 4 @ ISB 155 156 /* 157 * disable MMU stuff and caches 158 */ 159 mrc p15, 0, r0, c1, c0, 0 160 bic r0, r0, #0x00002000 @ clear bits 13 (--V-) 161 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) 162 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align 163 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB 164#ifdef CONFIG_SYS_ICACHE_OFF 165 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache 166#else 167 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache 168#endif 169 mcr p15, 0, r0, c1, c0, 0 170 171#ifdef CONFIG_ARM_ERRATA_716044 172 mrc p15, 0, r0, c1, c0, 0 @ read system control register 173 orr r0, r0, #1 << 11 @ set bit #11 174 mcr p15, 0, r0, c1, c0, 0 @ write system control register 175#endif 176 177#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072)) 178 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 179 orr r0, r0, #1 << 4 @ set bit #4 180 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 181#endif 182 183#ifdef CONFIG_ARM_ERRATA_743622 184 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 185 orr r0, r0, #1 << 6 @ set bit #6 186 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 187#endif 188 189#ifdef CONFIG_ARM_ERRATA_751472 190 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 191 orr r0, r0, #1 << 11 @ set bit #11 192 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 193#endif 194#ifdef CONFIG_ARM_ERRATA_761320 195 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 196 orr r0, r0, #1 << 21 @ set bit #21 197 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 198#endif 199 200#ifdef CONFIG_ARM_ERRATA_845369 201 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 202 orr r0, r0, #1 << 22 @ set bit #22 203 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 204#endif 205 206 mov r5, lr @ Store my Caller 207 mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR) 208 mov r3, r1, lsr #20 @ get variant field 209 and r3, r3, #0xf @ r3 has CPU variant 210 and r4, r1, #0xf @ r4 has CPU revision 211 mov r2, r3, lsl #4 @ shift variant field for combined value 212 orr r2, r4, r2 @ r2 has combined CPU variant + revision 213 214#ifdef CONFIG_ARM_ERRATA_798870 215 cmp r2, #0x30 @ Applies to lower than R3p0 216 bge skip_errata_798870 @ skip if not affected rev 217 cmp r2, #0x20 @ Applies to including and above R2p0 218 blt skip_errata_798870 @ skip if not affected rev 219 220 mrc p15, 1, r0, c15, c0, 0 @ read l2 aux ctrl reg 221 orr r0, r0, #1 << 7 @ Enable hazard-detect timeout 222 push {r1-r5} @ Save the cpu info registers 223 bl v7_arch_cp15_set_l2aux_ctrl 224 isb @ Recommended ISB after l2actlr update 225 pop {r1-r5} @ Restore the cpu info - fall through 226skip_errata_798870: 227#endif 228 229#ifdef CONFIG_ARM_ERRATA_801819 230 cmp r2, #0x24 @ Applies to lt including R2p4 231 bgt skip_errata_801819 @ skip if not affected rev 232 cmp r2, #0x20 @ Applies to including and above R2p0 233 blt skip_errata_801819 @ skip if not affected rev 234 mrc p15, 0, r0, c0, c0, 6 @ pick up REVIDR reg 235 and r0, r0, #1 << 3 @ check REVIDR[3] 236 cmp r0, #1 << 3 237 beq skip_errata_801819 @ skip erratum if REVIDR[3] is set 238 239 mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register 240 orr r0, r0, #3 << 27 @ Disables streaming. All write-allocate 241 @ lines allocate in the L1 or L2 cache. 242 orr r0, r0, #3 << 25 @ Disables streaming. All write-allocate 243 @ lines allocate in the L1 cache. 244 push {r1-r5} @ Save the cpu info registers 245 bl v7_arch_cp15_set_acr 246 pop {r1-r5} @ Restore the cpu info - fall through 247skip_errata_801819: 248#endif 249 250#ifdef CONFIG_ARM_ERRATA_454179 251 cmp r2, #0x21 @ Only on < r2p1 252 bge skip_errata_454179 253 254 mrc p15, 0, r0, c1, c0, 1 @ Read ACR 255 orr r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits 256 push {r1-r5} @ Save the cpu info registers 257 bl v7_arch_cp15_set_acr 258 pop {r1-r5} @ Restore the cpu info - fall through 259 260skip_errata_454179: 261#endif 262 263#ifdef CONFIG_ARM_ERRATA_430973 264 cmp r2, #0x21 @ Only on < r2p1 265 bge skip_errata_430973 266 267 mrc p15, 0, r0, c1, c0, 1 @ Read ACR 268 orr r0, r0, #(0x1 << 6) @ Set IBE bit 269 push {r1-r5} @ Save the cpu info registers 270 bl v7_arch_cp15_set_acr 271 pop {r1-r5} @ Restore the cpu info - fall through 272 273skip_errata_430973: 274#endif 275 276#ifdef CONFIG_ARM_ERRATA_621766 277 cmp r2, #0x21 @ Only on < r2p1 278 bge skip_errata_621766 279 280 mrc p15, 0, r0, c1, c0, 1 @ Read ACR 281 orr r0, r0, #(0x1 << 5) @ Set L1NEON bit 282 push {r1-r5} @ Save the cpu info registers 283 bl v7_arch_cp15_set_acr 284 pop {r1-r5} @ Restore the cpu info - fall through 285 286skip_errata_621766: 287#endif 288 289#ifdef CONFIG_ARM_ERRATA_725233 290 cmp r2, #0x21 @ Only on < r2p1 (Cortex A8) 291 bge skip_errata_725233 292 293 mrc p15, 1, r0, c9, c0, 2 @ Read L2ACR 294 orr r0, r0, #(0x1 << 27) @ L2 PLD data forwarding disable 295 push {r1-r5} @ Save the cpu info registers 296 bl v7_arch_cp15_set_l2aux_ctrl 297 pop {r1-r5} @ Restore the cpu info - fall through 298 299skip_errata_725233: 300#endif 301 302#ifdef CONFIG_ARM_ERRATA_852421 303 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 304 orr r0, r0, #1 << 24 @ set bit #24 305 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 306#endif 307 308#ifdef CONFIG_ARM_ERRATA_852423 309 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 310 orr r0, r0, #1 << 12 @ set bit #12 311 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 312#endif 313 314 mov pc, r5 @ back to my caller 315ENDPROC(cpu_init_cp15) 316 317#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ 318 !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) 319/************************************************************************* 320 * 321 * CPU_init_critical registers 322 * 323 * setup important registers 324 * setup memory timing 325 * 326 *************************************************************************/ 327ENTRY(cpu_init_crit) 328 /* 329 * Jump to board specific initialization... 330 * The Mask ROM will have already initialized 331 * basic memory. Go here to bump up clock rate and handle 332 * wake up conditions. 333 */ 334 b lowlevel_init @ go setup pll,mux,memory 335ENDPROC(cpu_init_crit) 336#endif 337