1/* 2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com> 12 * 13 * See file CREDITS for list of people who contributed to this 14 * project. 15 * 16 * This program is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation; either version 2 of 19 * the License, or (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 29 * MA 02111-1307 USA 30 */ 31 32#include <asm-offsets.h> 33#include <config.h> 34#include <version.h> 35#include <asm/system.h> 36 37.globl _start 38_start: b reset 39 ldr pc, _undefined_instruction 40 ldr pc, _software_interrupt 41 ldr pc, _prefetch_abort 42 ldr pc, _data_abort 43 ldr pc, _not_used 44 ldr pc, _irq 45 ldr pc, _fiq 46#ifdef CONFIG_SPL_BUILD 47_undefined_instruction: .word _undefined_instruction 48_software_interrupt: .word _software_interrupt 49_prefetch_abort: .word _prefetch_abort 50_data_abort: .word _data_abort 51_not_used: .word _not_used 52_irq: .word _irq 53_fiq: .word _fiq 54_pad: .word 0x12345678 /* now 16*4=64 */ 55#else 56_undefined_instruction: .word undefined_instruction 57_software_interrupt: .word software_interrupt 58_prefetch_abort: .word prefetch_abort 59_data_abort: .word data_abort 60_not_used: .word not_used 61_irq: .word irq 62_fiq: .word fiq 63_pad: .word 0x12345678 /* now 16*4=64 */ 64#endif /* CONFIG_SPL_BUILD */ 65 66.global _end_vect 67_end_vect: 68 69 .balignl 16,0xdeadbeef 70/************************************************************************* 71 * 72 * Startup Code (reset vector) 73 * 74 * do important init only if we don't start from memory! 75 * setup Memory and board specific bits prior to relocation. 76 * relocate armboot to ram 77 * setup stack 78 * 79 *************************************************************************/ 80 81.globl _TEXT_BASE 82_TEXT_BASE: 83 .word CONFIG_SYS_TEXT_BASE 84 85#ifdef CONFIG_TEGRA2 86/* 87 * Tegra2 uses 2 separate CPUs - the AVP (ARM7TDMI) and the CPU (dual A9s). 88 * U-Boot runs on the AVP first, setting things up for the CPU (PLLs, 89 * muxes, clocks, clamps, etc.). Then the AVP halts, and expects the CPU 90 * to pick up its reset vector, which points here. 91 */ 92.globl _armboot_start 93_armboot_start: 94 .word _start 95#endif 96 97/* 98 * These are defined in the board-specific linker script. 99 */ 100.globl _bss_start_ofs 101_bss_start_ofs: 102 .word __bss_start - _start 103 104.global _image_copy_end_ofs 105_image_copy_end_ofs: 106 .word __image_copy_end - _start 107 108.globl _bss_end_ofs 109_bss_end_ofs: 110 .word __bss_end__ - _start 111 112.globl _end_ofs 113_end_ofs: 114 .word _end - _start 115 116#ifdef CONFIG_USE_IRQ 117/* IRQ stack memory (calculated at run-time) */ 118.globl IRQ_STACK_START 119IRQ_STACK_START: 120 .word 0x0badc0de 121 122/* IRQ stack memory (calculated at run-time) */ 123.globl FIQ_STACK_START 124FIQ_STACK_START: 125 .word 0x0badc0de 126#endif 127 128/* IRQ stack memory (calculated at run-time) + 8 bytes */ 129.globl IRQ_STACK_START_IN 130IRQ_STACK_START_IN: 131 .word 0x0badc0de 132 133/* 134 * the actual reset code 135 */ 136 137reset: 138 bl save_boot_params 139 /* 140 * set the cpu to SVC32 mode 141 */ 142 mrs r0, cpsr 143 bic r0, r0, #0x1f 144 orr r0, r0, #0xd3 145 msr cpsr,r0 146 147/* 148 * Setup vector: 149 * (OMAP4 spl TEXT_BASE is not 32 byte aligned. 150 * Continue to use ROM code vector only in OMAP4 spl) 151 */ 152#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) 153 /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */ 154 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register 155 bic r0, #CR_V @ V = 0 156 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register 157 158 /* Set vector address in CP15 VBAR register */ 159 ldr r0, =_start 160 mcr p15, 0, r0, c12, c0, 0 @Set VBAR 161#endif 162 163#if defined(CONFIG_OMAP34XX) 164 /* Copy vectors to mask ROM indirect addr */ 165 adr r0, _start @ r0 <- current position of code 166 add r0, r0, #4 @ skip reset vector 167 mov r2, #64 @ r2 <- size to copy 168 add r2, r0, r2 @ r2 <- source end address 169 mov r1, #SRAM_OFFSET0 @ build vect addr 170 mov r3, #SRAM_OFFSET1 171 add r1, r1, r3 172 mov r3, #SRAM_OFFSET2 173 add r1, r1, r3 174next: 175 ldmia r0!, {r3 - r10} @ copy from source address [r0] 176 stmia r1!, {r3 - r10} @ copy to target address [r1] 177 cmp r0, r2 @ until source end address [r2] 178 bne next @ loop until equal */ 179#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT) 180 /* No need to copy/exec the clock code - DPLL adjust already done 181 * in NAND/oneNAND Boot. 182 */ 183 bl cpy_clk_code @ put dpll adjust code behind vectors 184#endif /* NAND Boot */ 185#endif 186 /* the mask ROM code should have PLL and others stable */ 187#ifndef CONFIG_SKIP_LOWLEVEL_INIT 188 bl cpu_init_crit 189#endif 190 191/* Set stackpointer in internal RAM to call board_init_f */ 192call_board_init_f: 193 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 194 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 195 ldr r0,=0x00000000 196 bl board_init_f 197 198/*------------------------------------------------------------------------------*/ 199 200/* 201 * void relocate_code (addr_sp, gd, addr_moni) 202 * 203 * This "function" does not return, instead it continues in RAM 204 * after relocating the monitor code. 205 * 206 */ 207 .globl relocate_code 208relocate_code: 209 mov r4, r0 /* save addr_sp */ 210 mov r5, r1 /* save addr of gd */ 211 mov r6, r2 /* save addr of destination */ 212 213 /* Set up the stack */ 214stack_setup: 215 mov sp, r4 216 217 adr r0, _start 218 cmp r0, r6 219 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ 220 beq clear_bss /* skip relocation */ 221 mov r1, r6 /* r1 <- scratch for copy_loop */ 222 ldr r3, _image_copy_end_ofs 223 add r2, r0, r3 /* r2 <- source end address */ 224 225copy_loop: 226 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 227 stmia r1!, {r9-r10} /* copy to target address [r1] */ 228 cmp r0, r2 /* until source end address [r2] */ 229 blo copy_loop 230 231#ifndef CONFIG_SPL_BUILD 232 /* 233 * fix .rel.dyn relocations 234 */ 235 ldr r0, _TEXT_BASE /* r0 <- Text base */ 236 sub r9, r6, r0 /* r9 <- relocation offset */ 237 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 238 add r10, r10, r0 /* r10 <- sym table in FLASH */ 239 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 240 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 241 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 242 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 243fixloop: 244 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 245 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 246 ldr r1, [r2, #4] 247 and r7, r1, #0xff 248 cmp r7, #23 /* relative fixup? */ 249 beq fixrel 250 cmp r7, #2 /* absolute fixup? */ 251 beq fixabs 252 /* ignore unknown type of fixup */ 253 b fixnext 254fixabs: 255 /* absolute fix: set location to (offset) symbol value */ 256 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 257 add r1, r10, r1 /* r1 <- address of symbol in table */ 258 ldr r1, [r1, #4] /* r1 <- symbol value */ 259 add r1, r1, r9 /* r1 <- relocated sym addr */ 260 b fixnext 261fixrel: 262 /* relative fix: increase location by offset */ 263 ldr r1, [r0] 264 add r1, r1, r9 265fixnext: 266 str r1, [r0] 267 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 268 cmp r2, r3 269 blo fixloop 270 b clear_bss 271_rel_dyn_start_ofs: 272 .word __rel_dyn_start - _start 273_rel_dyn_end_ofs: 274 .word __rel_dyn_end - _start 275_dynsym_start_ofs: 276 .word __dynsym_start - _start 277 278#endif /* #ifndef CONFIG_SPL_BUILD */ 279 280clear_bss: 281#ifdef CONFIG_SPL_BUILD 282 /* No relocation for SPL */ 283 ldr r0, =__bss_start 284 ldr r1, =__bss_end__ 285#else 286 ldr r0, _bss_start_ofs 287 ldr r1, _bss_end_ofs 288 mov r4, r6 /* reloc addr */ 289 add r0, r0, r4 290 add r1, r1, r4 291#endif 292 mov r2, #0x00000000 /* clear */ 293 294clbss_l:str r2, [r0] /* clear loop... */ 295 add r0, r0, #4 296 cmp r0, r1 297 bne clbss_l 298 299/* 300 * We are done. Do not return, instead branch to second part of board 301 * initialization, now running from RAM. 302 */ 303jump_2_ram: 304/* 305 * If I-cache is enabled invalidate it 306 */ 307#ifndef CONFIG_SYS_ICACHE_OFF 308 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 309 mcr p15, 0, r0, c7, c10, 4 @ DSB 310 mcr p15, 0, r0, c7, c5, 4 @ ISB 311#endif 312 ldr r0, _board_init_r_ofs 313 adr r1, _start 314 add lr, r0, r1 315 add lr, lr, r9 316 /* setup parameters for board_init_r */ 317 mov r0, r5 /* gd_t */ 318 mov r1, r6 /* dest_addr */ 319 /* jump to it ... */ 320 mov pc, lr 321 322_board_init_r_ofs: 323 .word board_init_r - _start 324 325 326#ifndef CONFIG_SKIP_LOWLEVEL_INIT 327/************************************************************************* 328 * 329 * CPU_init_critical registers 330 * 331 * setup important registers 332 * setup memory timing 333 * 334 *************************************************************************/ 335cpu_init_crit: 336 /* 337 * Invalidate L1 I/D 338 */ 339 mov r0, #0 @ set up for MCR 340 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs 341 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 342 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array 343 mcr p15, 0, r0, c7, c10, 4 @ DSB 344 mcr p15, 0, r0, c7, c5, 4 @ ISB 345 346 /* 347 * disable MMU stuff and caches 348 */ 349 mrc p15, 0, r0, c1, c0, 0 350 bic r0, r0, #0x00002000 @ clear bits 13 (--V-) 351 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) 352 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align 353 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB 354#ifdef CONFIG_SYS_ICACHE_OFF 355 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache 356#else 357 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache 358#endif 359 mcr p15, 0, r0, c1, c0, 0 360 361 /* 362 * Jump to board specific initialization... 363 * The Mask ROM will have already initialized 364 * basic memory. Go here to bump up clock rate and handle 365 * wake up conditions. 366 */ 367 mov ip, lr @ persevere link reg across call 368 bl lowlevel_init @ go setup pll,mux,memory 369 mov lr, ip @ restore link 370 mov pc, lr @ back to my caller 371#endif 372 373#ifndef CONFIG_SPL_BUILD 374/* 375 ************************************************************************* 376 * 377 * Interrupt handling 378 * 379 ************************************************************************* 380 */ 381@ 382@ IRQ stack frame. 383@ 384#define S_FRAME_SIZE 72 385 386#define S_OLD_R0 68 387#define S_PSR 64 388#define S_PC 60 389#define S_LR 56 390#define S_SP 52 391 392#define S_IP 48 393#define S_FP 44 394#define S_R10 40 395#define S_R9 36 396#define S_R8 32 397#define S_R7 28 398#define S_R6 24 399#define S_R5 20 400#define S_R4 16 401#define S_R3 12 402#define S_R2 8 403#define S_R1 4 404#define S_R0 0 405 406#define MODE_SVC 0x13 407#define I_BIT 0x80 408 409/* 410 * use bad_save_user_regs for abort/prefetch/undef/swi ... 411 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 412 */ 413 414 .macro bad_save_user_regs 415 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current 416 @ user stack 417 stmia sp, {r0 - r12} @ Save user registers (now in 418 @ svc mode) r0-r12 419 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort 420 @ stack 421 ldmia r2, {r2 - r3} @ get values for "aborted" pc 422 @ and cpsr (into parm regs) 423 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 424 425 add r5, sp, #S_SP 426 mov r1, lr 427 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 428 mov r0, sp @ save current stack into r0 429 @ (param register) 430 .endm 431 432 .macro irq_save_user_regs 433 sub sp, sp, #S_FRAME_SIZE 434 stmia sp, {r0 - r12} @ Calling r0-r12 435 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !! 436 @ a reserved stack spot would 437 @ be good. 438 stmdb r8, {sp, lr}^ @ Calling SP, LR 439 str lr, [r8, #0] @ Save calling PC 440 mrs r6, spsr 441 str r6, [r8, #4] @ Save CPSR 442 str r0, [r8, #8] @ Save OLD_R0 443 mov r0, sp 444 .endm 445 446 .macro irq_restore_user_regs 447 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 448 mov r0, r0 449 ldr lr, [sp, #S_PC] @ Get PC 450 add sp, sp, #S_FRAME_SIZE 451 subs pc, lr, #4 @ return & move spsr_svc into 452 @ cpsr 453 .endm 454 455 .macro get_bad_stack 456 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter 457 @ in banked mode) 458 459 str lr, [r13] @ save caller lr in position 0 460 @ of saved stack 461 mrs lr, spsr @ get the spsr 462 str lr, [r13, #4] @ save spsr in position 1 of 463 @ saved stack 464 465 mov r13, #MODE_SVC @ prepare SVC-Mode 466 @ msr spsr_c, r13 467 msr spsr, r13 @ switch modes, make sure 468 @ moves will execute 469 mov lr, pc @ capture return pc 470 movs pc, lr @ jump to next instruction & 471 @ switch modes. 472 .endm 473 474 .macro get_bad_stack_swi 475 sub r13, r13, #4 @ space on current stack for 476 @ scratch reg. 477 str r0, [r13] @ save R0's value. 478 ldr r0, IRQ_STACK_START_IN @ get data regions start 479 @ spots for abort stack 480 str lr, [r0] @ save caller lr in position 0 481 @ of saved stack 482 mrs r0, spsr @ get the spsr 483 str lr, [r0, #4] @ save spsr in position 1 of 484 @ saved stack 485 ldr r0, [r13] @ restore r0 486 add r13, r13, #4 @ pop stack entry 487 .endm 488 489 .macro get_irq_stack @ setup IRQ stack 490 ldr sp, IRQ_STACK_START 491 .endm 492 493 .macro get_fiq_stack @ setup FIQ stack 494 ldr sp, FIQ_STACK_START 495 .endm 496 497/* 498 * exception handlers 499 */ 500 .align 5 501undefined_instruction: 502 get_bad_stack 503 bad_save_user_regs 504 bl do_undefined_instruction 505 506 .align 5 507software_interrupt: 508 get_bad_stack_swi 509 bad_save_user_regs 510 bl do_software_interrupt 511 512 .align 5 513prefetch_abort: 514 get_bad_stack 515 bad_save_user_regs 516 bl do_prefetch_abort 517 518 .align 5 519data_abort: 520 get_bad_stack 521 bad_save_user_regs 522 bl do_data_abort 523 524 .align 5 525not_used: 526 get_bad_stack 527 bad_save_user_regs 528 bl do_not_used 529 530#ifdef CONFIG_USE_IRQ 531 532 .align 5 533irq: 534 get_irq_stack 535 irq_save_user_regs 536 bl do_irq 537 irq_restore_user_regs 538 539 .align 5 540fiq: 541 get_fiq_stack 542 /* someone ought to write a more effective fiq_save_user_regs */ 543 irq_save_user_regs 544 bl do_fiq 545 irq_restore_user_regs 546 547#else 548 549 .align 5 550irq: 551 get_bad_stack 552 bad_save_user_regs 553 bl do_irq 554 555 .align 5 556fiq: 557 get_bad_stack 558 bad_save_user_regs 559 bl do_fiq 560 561#endif /* CONFIG_USE_IRQ */ 562#endif /* CONFIG_SPL_BUILD */ 563