1/* 2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com> 12 * 13 * See file CREDITS for list of people who contributed to this 14 * project. 15 * 16 * This program is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation; either version 2 of 19 * the License, or (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 29 * MA 02111-1307 USA 30 */ 31 32#include <asm-offsets.h> 33#include <config.h> 34#include <version.h> 35#include <asm/system.h> 36 37.globl _start 38_start: b reset 39 ldr pc, _undefined_instruction 40 ldr pc, _software_interrupt 41 ldr pc, _prefetch_abort 42 ldr pc, _data_abort 43 ldr pc, _not_used 44 ldr pc, _irq 45 ldr pc, _fiq 46#ifdef CONFIG_SPL_BUILD 47_undefined_instruction: .word _undefined_instruction 48_software_interrupt: .word _software_interrupt 49_prefetch_abort: .word _prefetch_abort 50_data_abort: .word _data_abort 51_not_used: .word _not_used 52_irq: .word _irq 53_fiq: .word _fiq 54_pad: .word 0x12345678 /* now 16*4=64 */ 55#else 56_undefined_instruction: .word undefined_instruction 57_software_interrupt: .word software_interrupt 58_prefetch_abort: .word prefetch_abort 59_data_abort: .word data_abort 60_not_used: .word not_used 61_irq: .word irq 62_fiq: .word fiq 63_pad: .word 0x12345678 /* now 16*4=64 */ 64#endif /* CONFIG_SPL_BUILD */ 65 66.global _end_vect 67_end_vect: 68 69 .balignl 16,0xdeadbeef 70/************************************************************************* 71 * 72 * Startup Code (reset vector) 73 * 74 * do important init only if we don't start from memory! 75 * setup Memory and board specific bits prior to relocation. 76 * relocate armboot to ram 77 * setup stack 78 * 79 *************************************************************************/ 80 81.globl _TEXT_BASE 82_TEXT_BASE: 83 .word CONFIG_SYS_TEXT_BASE 84 85#ifdef CONFIG_TEGRA2 86/* 87 * Tegra2 uses 2 separate CPUs - the AVP (ARM7TDMI) and the CPU (dual A9s). 88 * U-Boot runs on the AVP first, setting things up for the CPU (PLLs, 89 * muxes, clocks, clamps, etc.). Then the AVP halts, and expects the CPU 90 * to pick up its reset vector, which points here. 91 */ 92.globl _armboot_start 93_armboot_start: 94 .word _start 95#endif 96 97/* 98 * These are defined in the board-specific linker script. 99 */ 100.globl _bss_start_ofs 101_bss_start_ofs: 102 .word __bss_start - _start 103 104.global _image_copy_end_ofs 105_image_copy_end_ofs: 106 .word __image_copy_end - _start 107 108.globl _bss_end_ofs 109_bss_end_ofs: 110 .word __bss_end__ - _start 111 112.globl _end_ofs 113_end_ofs: 114 .word _end - _start 115 116#ifdef CONFIG_USE_IRQ 117/* IRQ stack memory (calculated at run-time) */ 118.globl IRQ_STACK_START 119IRQ_STACK_START: 120 .word 0x0badc0de 121 122/* IRQ stack memory (calculated at run-time) */ 123.globl FIQ_STACK_START 124FIQ_STACK_START: 125 .word 0x0badc0de 126#endif 127 128/* IRQ stack memory (calculated at run-time) + 8 bytes */ 129.globl IRQ_STACK_START_IN 130IRQ_STACK_START_IN: 131 .word 0x0badc0de 132 133/* 134 * the actual reset code 135 */ 136 137reset: 138 bl save_boot_params 139 /* 140 * set the cpu to SVC32 mode 141 */ 142 mrs r0, cpsr 143 bic r0, r0, #0x1f 144 orr r0, r0, #0xd3 145 msr cpsr,r0 146 147/* 148 * Setup vector: 149 * (OMAP4 spl TEXT_BASE is not 32 byte aligned. 150 * Continue to use ROM code vector only in OMAP4 spl) 151 */ 152#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) 153 /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */ 154 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register 155 bic r0, #CR_V @ V = 0 156 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register 157 158 /* Set vector address in CP15 VBAR register */ 159 ldr r0, =_start 160 mcr p15, 0, r0, c12, c0, 0 @Set VBAR 161#endif 162 163 /* the mask ROM code should have PLL and others stable */ 164#ifndef CONFIG_SKIP_LOWLEVEL_INIT 165 bl cpu_init_cp15 166 bl cpu_init_crit 167#endif 168 169/* Set stackpointer in internal RAM to call board_init_f */ 170call_board_init_f: 171 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 172 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 173 ldr r0,=0x00000000 174 bl board_init_f 175 176/*------------------------------------------------------------------------------*/ 177 178/* 179 * void relocate_code (addr_sp, gd, addr_moni) 180 * 181 * This "function" does not return, instead it continues in RAM 182 * after relocating the monitor code. 183 * 184 */ 185 .globl relocate_code 186relocate_code: 187 mov r4, r0 /* save addr_sp */ 188 mov r5, r1 /* save addr of gd */ 189 mov r6, r2 /* save addr of destination */ 190 191 /* Set up the stack */ 192stack_setup: 193 mov sp, r4 194 195 adr r0, _start 196 cmp r0, r6 197 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ 198 beq clear_bss /* skip relocation */ 199 mov r1, r6 /* r1 <- scratch for copy_loop */ 200 ldr r3, _image_copy_end_ofs 201 add r2, r0, r3 /* r2 <- source end address */ 202 203copy_loop: 204 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 205 stmia r1!, {r9-r10} /* copy to target address [r1] */ 206 cmp r0, r2 /* until source end address [r2] */ 207 blo copy_loop 208 209#ifndef CONFIG_SPL_BUILD 210 /* 211 * fix .rel.dyn relocations 212 */ 213 ldr r0, _TEXT_BASE /* r0 <- Text base */ 214 sub r9, r6, r0 /* r9 <- relocation offset */ 215 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 216 add r10, r10, r0 /* r10 <- sym table in FLASH */ 217 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 218 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 219 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 220 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 221fixloop: 222 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 223 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 224 ldr r1, [r2, #4] 225 and r7, r1, #0xff 226 cmp r7, #23 /* relative fixup? */ 227 beq fixrel 228 cmp r7, #2 /* absolute fixup? */ 229 beq fixabs 230 /* ignore unknown type of fixup */ 231 b fixnext 232fixabs: 233 /* absolute fix: set location to (offset) symbol value */ 234 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 235 add r1, r10, r1 /* r1 <- address of symbol in table */ 236 ldr r1, [r1, #4] /* r1 <- symbol value */ 237 add r1, r1, r9 /* r1 <- relocated sym addr */ 238 b fixnext 239fixrel: 240 /* relative fix: increase location by offset */ 241 ldr r1, [r0] 242 add r1, r1, r9 243fixnext: 244 str r1, [r0] 245 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 246 cmp r2, r3 247 blo fixloop 248 b clear_bss 249_rel_dyn_start_ofs: 250 .word __rel_dyn_start - _start 251_rel_dyn_end_ofs: 252 .word __rel_dyn_end - _start 253_dynsym_start_ofs: 254 .word __dynsym_start - _start 255 256#endif /* #ifndef CONFIG_SPL_BUILD */ 257 258clear_bss: 259#ifdef CONFIG_SPL_BUILD 260 /* No relocation for SPL */ 261 ldr r0, =__bss_start 262 ldr r1, =__bss_end__ 263#else 264 ldr r0, _bss_start_ofs 265 ldr r1, _bss_end_ofs 266 mov r4, r6 /* reloc addr */ 267 add r0, r0, r4 268 add r1, r1, r4 269#endif 270 mov r2, #0x00000000 /* clear */ 271 272clbss_l:str r2, [r0] /* clear loop... */ 273 add r0, r0, #4 274 cmp r0, r1 275 bne clbss_l 276 277/* 278 * We are done. Do not return, instead branch to second part of board 279 * initialization, now running from RAM. 280 */ 281jump_2_ram: 282/* 283 * If I-cache is enabled invalidate it 284 */ 285#ifndef CONFIG_SYS_ICACHE_OFF 286 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 287 mcr p15, 0, r0, c7, c10, 4 @ DSB 288 mcr p15, 0, r0, c7, c5, 4 @ ISB 289#endif 290 ldr r0, _board_init_r_ofs 291 adr r1, _start 292 add lr, r0, r1 293 add lr, lr, r9 294 /* setup parameters for board_init_r */ 295 mov r0, r5 /* gd_t */ 296 mov r1, r6 /* dest_addr */ 297 /* jump to it ... */ 298 mov pc, lr 299 300_board_init_r_ofs: 301 .word board_init_r - _start 302 303/************************************************************************* 304 * 305 * cpu_init_cp15 306 * 307 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless 308 * CONFIG_SYS_ICACHE_OFF is defined. 309 * 310 *************************************************************************/ 311.globl cpu_init_cp15 312cpu_init_cp15: 313 /* 314 * Invalidate L1 I/D 315 */ 316 mov r0, #0 @ set up for MCR 317 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs 318 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 319 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array 320 mcr p15, 0, r0, c7, c10, 4 @ DSB 321 mcr p15, 0, r0, c7, c5, 4 @ ISB 322 323 /* 324 * disable MMU stuff and caches 325 */ 326 mrc p15, 0, r0, c1, c0, 0 327 bic r0, r0, #0x00002000 @ clear bits 13 (--V-) 328 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) 329 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align 330 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB 331#ifdef CONFIG_SYS_ICACHE_OFF 332 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache 333#else 334 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache 335#endif 336 mcr p15, 0, r0, c1, c0, 0 337 mov pc, lr @ back to my caller 338 339 340#ifndef CONFIG_SKIP_LOWLEVEL_INIT 341/************************************************************************* 342 * 343 * CPU_init_critical registers 344 * 345 * setup important registers 346 * setup memory timing 347 * 348 *************************************************************************/ 349cpu_init_crit: 350 /* 351 * Jump to board specific initialization... 352 * The Mask ROM will have already initialized 353 * basic memory. Go here to bump up clock rate and handle 354 * wake up conditions. 355 */ 356 mov ip, lr @ persevere link reg across call 357 bl lowlevel_init @ go setup pll,mux,memory 358 mov lr, ip @ restore link 359 mov pc, lr @ back to my caller 360#endif 361 362#ifndef CONFIG_SPL_BUILD 363/* 364 ************************************************************************* 365 * 366 * Interrupt handling 367 * 368 ************************************************************************* 369 */ 370@ 371@ IRQ stack frame. 372@ 373#define S_FRAME_SIZE 72 374 375#define S_OLD_R0 68 376#define S_PSR 64 377#define S_PC 60 378#define S_LR 56 379#define S_SP 52 380 381#define S_IP 48 382#define S_FP 44 383#define S_R10 40 384#define S_R9 36 385#define S_R8 32 386#define S_R7 28 387#define S_R6 24 388#define S_R5 20 389#define S_R4 16 390#define S_R3 12 391#define S_R2 8 392#define S_R1 4 393#define S_R0 0 394 395#define MODE_SVC 0x13 396#define I_BIT 0x80 397 398/* 399 * use bad_save_user_regs for abort/prefetch/undef/swi ... 400 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 401 */ 402 403 .macro bad_save_user_regs 404 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current 405 @ user stack 406 stmia sp, {r0 - r12} @ Save user registers (now in 407 @ svc mode) r0-r12 408 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort 409 @ stack 410 ldmia r2, {r2 - r3} @ get values for "aborted" pc 411 @ and cpsr (into parm regs) 412 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 413 414 add r5, sp, #S_SP 415 mov r1, lr 416 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 417 mov r0, sp @ save current stack into r0 418 @ (param register) 419 .endm 420 421 .macro irq_save_user_regs 422 sub sp, sp, #S_FRAME_SIZE 423 stmia sp, {r0 - r12} @ Calling r0-r12 424 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !! 425 @ a reserved stack spot would 426 @ be good. 427 stmdb r8, {sp, lr}^ @ Calling SP, LR 428 str lr, [r8, #0] @ Save calling PC 429 mrs r6, spsr 430 str r6, [r8, #4] @ Save CPSR 431 str r0, [r8, #8] @ Save OLD_R0 432 mov r0, sp 433 .endm 434 435 .macro irq_restore_user_regs 436 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 437 mov r0, r0 438 ldr lr, [sp, #S_PC] @ Get PC 439 add sp, sp, #S_FRAME_SIZE 440 subs pc, lr, #4 @ return & move spsr_svc into 441 @ cpsr 442 .endm 443 444 .macro get_bad_stack 445 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter 446 @ in banked mode) 447 448 str lr, [r13] @ save caller lr in position 0 449 @ of saved stack 450 mrs lr, spsr @ get the spsr 451 str lr, [r13, #4] @ save spsr in position 1 of 452 @ saved stack 453 454 mov r13, #MODE_SVC @ prepare SVC-Mode 455 @ msr spsr_c, r13 456 msr spsr, r13 @ switch modes, make sure 457 @ moves will execute 458 mov lr, pc @ capture return pc 459 movs pc, lr @ jump to next instruction & 460 @ switch modes. 461 .endm 462 463 .macro get_bad_stack_swi 464 sub r13, r13, #4 @ space on current stack for 465 @ scratch reg. 466 str r0, [r13] @ save R0's value. 467 ldr r0, IRQ_STACK_START_IN @ get data regions start 468 @ spots for abort stack 469 str lr, [r0] @ save caller lr in position 0 470 @ of saved stack 471 mrs r0, spsr @ get the spsr 472 str lr, [r0, #4] @ save spsr in position 1 of 473 @ saved stack 474 ldr r0, [r13] @ restore r0 475 add r13, r13, #4 @ pop stack entry 476 .endm 477 478 .macro get_irq_stack @ setup IRQ stack 479 ldr sp, IRQ_STACK_START 480 .endm 481 482 .macro get_fiq_stack @ setup FIQ stack 483 ldr sp, FIQ_STACK_START 484 .endm 485 486/* 487 * exception handlers 488 */ 489 .align 5 490undefined_instruction: 491 get_bad_stack 492 bad_save_user_regs 493 bl do_undefined_instruction 494 495 .align 5 496software_interrupt: 497 get_bad_stack_swi 498 bad_save_user_regs 499 bl do_software_interrupt 500 501 .align 5 502prefetch_abort: 503 get_bad_stack 504 bad_save_user_regs 505 bl do_prefetch_abort 506 507 .align 5 508data_abort: 509 get_bad_stack 510 bad_save_user_regs 511 bl do_data_abort 512 513 .align 5 514not_used: 515 get_bad_stack 516 bad_save_user_regs 517 bl do_not_used 518 519#ifdef CONFIG_USE_IRQ 520 521 .align 5 522irq: 523 get_irq_stack 524 irq_save_user_regs 525 bl do_irq 526 irq_restore_user_regs 527 528 .align 5 529fiq: 530 get_fiq_stack 531 /* someone ought to write a more effective fiq_save_user_regs */ 532 irq_save_user_regs 533 bl do_fiq 534 irq_restore_user_regs 535 536#else 537 538 .align 5 539irq: 540 get_bad_stack 541 bad_save_user_regs 542 bl do_irq 543 544 .align 5 545fiq: 546 get_bad_stack 547 bad_save_user_regs 548 bl do_fiq 549 550#endif /* CONFIG_USE_IRQ */ 551#endif /* CONFIG_SPL_BUILD */ 552