1/* 2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com> 12 * 13 * SPDX-License-Identifier: GPL-2.0+ 14 */ 15 16#include <asm-offsets.h> 17#include <config.h> 18#include <asm/system.h> 19#include <linux/linkage.h> 20#include <asm/armv7.h> 21 22/************************************************************************* 23 * 24 * Startup Code (reset vector) 25 * 26 * Do important init only if we don't start from memory! 27 * Setup memory and board specific bits prior to relocation. 28 * Relocate armboot to ram. Setup stack. 29 * 30 *************************************************************************/ 31 32 .globl reset 33 .globl save_boot_params_ret 34 .type save_boot_params_ret,%function 35#ifdef CONFIG_ARMV7_LPAE 36 .global switch_to_hypervisor_ret 37#endif 38 39reset: 40 /* Allow the board to save important registers */ 41 b save_boot_params 42save_boot_params_ret: 43#ifdef CONFIG_ARMV7_LPAE 44/* 45 * check for Hypervisor support 46 */ 47 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 48 and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits 49 cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT) 50 beq switch_to_hypervisor 51switch_to_hypervisor_ret: 52#endif 53 /* 54 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode, 55 * except if in HYP mode already 56 */ 57 mrs r0, cpsr 58 and r1, r0, #0x1f @ mask mode bits 59 teq r1, #0x1a @ test for HYP mode 60 bicne r0, r0, #0x1f @ clear all mode bits 61 orrne r0, r0, #0x13 @ set SVC mode 62 orr r0, r0, #0xc0 @ disable FIQ and IRQ 63 msr cpsr,r0 64 65 /* Enable ACTLR.SMP bit */ 66 mrc p15, 0, r0, c1, c0, 1 67 orr r0, r0, #(1 << 6) @ Enable ACTLR.SMP bit 68 mcr p15, 0, r0, c1, c0, 1 69 70/* 71 * Setup vector: 72 * (OMAP4 spl TEXT_BASE is not 32 byte aligned. 73 * Continue to use ROM code vector only in OMAP4 spl) 74 */ 75#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) 76 /* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */ 77 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register 78 bic r0, #CR_V @ V = 0 79 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register 80 81 /* Set vector address in CP15 VBAR register */ 82 ldr r0, =_start 83 mcr p15, 0, r0, c12, c0, 0 @Set VBAR 84#endif 85 86 /* the mask ROM code should have PLL and others stable */ 87#ifndef CONFIG_SKIP_LOWLEVEL_INIT 88 bl cpu_init_cp15 89#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY 90 bl cpu_init_crit 91#endif 92#endif 93 94 bl _main 95 96/*------------------------------------------------------------------------------*/ 97 98ENTRY(c_runtime_cpu_setup) 99/* 100 * If I-cache is enabled invalidate it 101 */ 102#ifndef CONFIG_SYS_ICACHE_OFF 103 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 104 mcr p15, 0, r0, c7, c10, 4 @ DSB 105 mcr p15, 0, r0, c7, c5, 4 @ ISB 106#endif 107 108 bx lr 109 110ENDPROC(c_runtime_cpu_setup) 111 112/************************************************************************* 113 * 114 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) 115 * __attribute__((weak)); 116 * 117 * Stack pointer is not yet initialized at this moment 118 * Don't save anything to stack even if compiled with -O0 119 * 120 *************************************************************************/ 121ENTRY(save_boot_params) 122 b save_boot_params_ret @ back to my caller 123ENDPROC(save_boot_params) 124 .weak save_boot_params 125 126#ifdef CONFIG_ARMV7_LPAE 127ENTRY(switch_to_hypervisor) 128 b switch_to_hypervisor_ret 129ENDPROC(switch_to_hypervisor) 130 .weak switch_to_hypervisor 131#endif 132 133/************************************************************************* 134 * 135 * cpu_init_cp15 136 * 137 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless 138 * CONFIG_SYS_ICACHE_OFF is defined. 139 * 140 *************************************************************************/ 141ENTRY(cpu_init_cp15) 142 /* 143 * Invalidate L1 I/D 144 */ 145 mov r0, #0 @ set up for MCR 146 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs 147 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 148 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array 149 mcr p15, 0, r0, c7, c10, 4 @ DSB 150 mcr p15, 0, r0, c7, c5, 4 @ ISB 151 152 /* 153 * disable MMU stuff and caches 154 */ 155 mrc p15, 0, r0, c1, c0, 0 156 bic r0, r0, #0x00002000 @ clear bits 13 (--V-) 157 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) 158 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align 159 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB 160#ifdef CONFIG_SYS_ICACHE_OFF 161 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache 162#else 163 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache 164#endif 165 mcr p15, 0, r0, c1, c0, 0 166 167#ifdef CONFIG_ARM_ERRATA_716044 168 mrc p15, 0, r0, c1, c0, 0 @ read system control register 169 orr r0, r0, #1 << 11 @ set bit #11 170 mcr p15, 0, r0, c1, c0, 0 @ write system control register 171#endif 172 173#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072)) 174 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 175 orr r0, r0, #1 << 4 @ set bit #4 176 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 177#endif 178 179#ifdef CONFIG_ARM_ERRATA_743622 180 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 181 orr r0, r0, #1 << 6 @ set bit #6 182 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 183#endif 184 185#ifdef CONFIG_ARM_ERRATA_751472 186 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 187 orr r0, r0, #1 << 11 @ set bit #11 188 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 189#endif 190#ifdef CONFIG_ARM_ERRATA_761320 191 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 192 orr r0, r0, #1 << 21 @ set bit #21 193 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 194#endif 195 196#ifdef CONFIG_ARM_ERRATA_845369 197 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 198 orr r0, r0, #1 << 22 @ set bit #22 199 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 200#endif 201 202 mov r5, lr @ Store my Caller 203 mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR) 204 mov r3, r1, lsr #20 @ get variant field 205 and r3, r3, #0xf @ r3 has CPU variant 206 and r4, r1, #0xf @ r4 has CPU revision 207 mov r2, r3, lsl #4 @ shift variant field for combined value 208 orr r2, r4, r2 @ r2 has combined CPU variant + revision 209 210#ifdef CONFIG_ARM_ERRATA_798870 211 cmp r2, #0x30 @ Applies to lower than R3p0 212 bge skip_errata_798870 @ skip if not affected rev 213 cmp r2, #0x20 @ Applies to including and above R2p0 214 blt skip_errata_798870 @ skip if not affected rev 215 216 mrc p15, 1, r0, c15, c0, 0 @ read l2 aux ctrl reg 217 orr r0, r0, #1 << 7 @ Enable hazard-detect timeout 218 push {r1-r5} @ Save the cpu info registers 219 bl v7_arch_cp15_set_l2aux_ctrl 220 isb @ Recommended ISB after l2actlr update 221 pop {r1-r5} @ Restore the cpu info - fall through 222skip_errata_798870: 223#endif 224 225#ifdef CONFIG_ARM_ERRATA_801819 226 cmp r2, #0x24 @ Applies to lt including R2p4 227 bgt skip_errata_801819 @ skip if not affected rev 228 cmp r2, #0x20 @ Applies to including and above R2p0 229 blt skip_errata_801819 @ skip if not affected rev 230 mrc p15, 0, r0, c0, c0, 6 @ pick up REVIDR reg 231 and r0, r0, #1 << 3 @ check REVIDR[3] 232 cmp r0, #1 << 3 233 beq skip_errata_801819 @ skip erratum if REVIDR[3] is set 234 235 mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register 236 orr r0, r0, #3 << 27 @ Disables streaming. All write-allocate 237 @ lines allocate in the L1 or L2 cache. 238 orr r0, r0, #3 << 25 @ Disables streaming. All write-allocate 239 @ lines allocate in the L1 cache. 240 push {r1-r5} @ Save the cpu info registers 241 bl v7_arch_cp15_set_acr 242 pop {r1-r5} @ Restore the cpu info - fall through 243skip_errata_801819: 244#endif 245 246#ifdef CONFIG_ARM_ERRATA_454179 247 cmp r2, #0x21 @ Only on < r2p1 248 bge skip_errata_454179 249 250 mrc p15, 0, r0, c1, c0, 1 @ Read ACR 251 orr r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits 252 push {r1-r5} @ Save the cpu info registers 253 bl v7_arch_cp15_set_acr 254 pop {r1-r5} @ Restore the cpu info - fall through 255 256skip_errata_454179: 257#endif 258 259#ifdef CONFIG_ARM_ERRATA_430973 260 cmp r2, #0x21 @ Only on < r2p1 261 bge skip_errata_430973 262 263 mrc p15, 0, r0, c1, c0, 1 @ Read ACR 264 orr r0, r0, #(0x1 << 6) @ Set IBE bit 265 push {r1-r5} @ Save the cpu info registers 266 bl v7_arch_cp15_set_acr 267 pop {r1-r5} @ Restore the cpu info - fall through 268 269skip_errata_430973: 270#endif 271 272#ifdef CONFIG_ARM_ERRATA_621766 273 cmp r2, #0x21 @ Only on < r2p1 274 bge skip_errata_621766 275 276 mrc p15, 0, r0, c1, c0, 1 @ Read ACR 277 orr r0, r0, #(0x1 << 5) @ Set L1NEON bit 278 push {r1-r5} @ Save the cpu info registers 279 bl v7_arch_cp15_set_acr 280 pop {r1-r5} @ Restore the cpu info - fall through 281 282skip_errata_621766: 283#endif 284 285#ifdef CONFIG_ARM_ERRATA_725233 286 cmp r2, #0x21 @ Only on < r2p1 (Cortex A8) 287 bge skip_errata_725233 288 289 mrc p15, 1, r0, c9, c0, 2 @ Read L2ACR 290 orr r0, r0, #(0x1 << 27) @ L2 PLD data forwarding disable 291 push {r1-r5} @ Save the cpu info registers 292 bl v7_arch_cp15_set_l2aux_ctrl 293 pop {r1-r5} @ Restore the cpu info - fall through 294 295skip_errata_725233: 296#endif 297 298#ifdef CONFIG_ARM_ERRATA_852421 299 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 300 orr r0, r0, #1 << 24 @ set bit #24 301 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 302#endif 303 304#ifdef CONFIG_ARM_ERRATA_852423 305 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 306 orr r0, r0, #1 << 12 @ set bit #12 307 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 308#endif 309 310 mov pc, r5 @ back to my caller 311ENDPROC(cpu_init_cp15) 312 313#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ 314 !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) 315/************************************************************************* 316 * 317 * CPU_init_critical registers 318 * 319 * setup important registers 320 * setup memory timing 321 * 322 *************************************************************************/ 323ENTRY(cpu_init_crit) 324 /* 325 * Jump to board specific initialization... 326 * The Mask ROM will have already initialized 327 * basic memory. Go here to bump up clock rate and handle 328 * wake up conditions. 329 */ 330 b lowlevel_init @ go setup pll,mux,memory 331ENDPROC(cpu_init_crit) 332#endif 333