1/* 2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com> 12 * 13 * SPDX-License-Identifier: GPL-2.0+ 14 */ 15 16#include <asm-offsets.h> 17#include <config.h> 18#include <version.h> 19#include <asm/system.h> 20#include <linux/linkage.h> 21 22/************************************************************************* 23 * 24 * Startup Code (reset vector) 25 * 26 * do important init only if we don't start from memory! 27 * setup Memory and board specific bits prior to relocation. 28 * relocate armboot to ram 29 * setup stack 30 * 31 *************************************************************************/ 32 33 .globl reset 34 .globl save_boot_params_ret 35 36reset: 37 /* Allow the board to save important registers */ 38 b save_boot_params 39save_boot_params_ret: 40 /* 41 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode, 42 * except if in HYP mode already 43 */ 44 mrs r0, cpsr 45 and r1, r0, #0x1f @ mask mode bits 46 teq r1, #0x1a @ test for HYP mode 47 bicne r0, r0, #0x1f @ clear all mode bits 48 orrne r0, r0, #0x13 @ set SVC mode 49 orr r0, r0, #0xc0 @ disable FIQ and IRQ 50 msr cpsr,r0 51 52/* 53 * Setup vector: 54 * (OMAP4 spl TEXT_BASE is not 32 byte aligned. 55 * Continue to use ROM code vector only in OMAP4 spl) 56 */ 57#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) 58 /* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */ 59 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register 60 bic r0, #CR_V @ V = 0 61 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register 62 63 /* Set vector address in CP15 VBAR register */ 64 ldr r0, =_start 65 mcr p15, 0, r0, c12, c0, 0 @Set VBAR 66#endif 67 68 /* the mask ROM code should have PLL and others stable */ 69#ifndef CONFIG_SKIP_LOWLEVEL_INIT 70 bl cpu_init_cp15 71 bl cpu_init_crit 72#endif 73 74 bl _main 75 76/*------------------------------------------------------------------------------*/ 77 78ENTRY(c_runtime_cpu_setup) 79/* 80 * If I-cache is enabled invalidate it 81 */ 82#ifndef CONFIG_SYS_ICACHE_OFF 83 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 84 mcr p15, 0, r0, c7, c10, 4 @ DSB 85 mcr p15, 0, r0, c7, c5, 4 @ ISB 86#endif 87 88 bx lr 89 90ENDPROC(c_runtime_cpu_setup) 91 92/************************************************************************* 93 * 94 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) 95 * __attribute__((weak)); 96 * 97 * Stack pointer is not yet initialized at this moment 98 * Don't save anything to stack even if compiled with -O0 99 * 100 *************************************************************************/ 101ENTRY(save_boot_params) 102 b save_boot_params_ret @ back to my caller 103ENDPROC(save_boot_params) 104 .weak save_boot_params 105 106/************************************************************************* 107 * 108 * cpu_init_cp15 109 * 110 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless 111 * CONFIG_SYS_ICACHE_OFF is defined. 112 * 113 *************************************************************************/ 114ENTRY(cpu_init_cp15) 115 /* 116 * Invalidate L1 I/D 117 */ 118 mov r0, #0 @ set up for MCR 119 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs 120 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 121 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array 122 mcr p15, 0, r0, c7, c10, 4 @ DSB 123 mcr p15, 0, r0, c7, c5, 4 @ ISB 124 125 /* 126 * disable MMU stuff and caches 127 */ 128 mrc p15, 0, r0, c1, c0, 0 129 bic r0, r0, #0x00002000 @ clear bits 13 (--V-) 130 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) 131 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align 132 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB 133#ifdef CONFIG_SYS_ICACHE_OFF 134 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache 135#else 136 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache 137#endif 138 mcr p15, 0, r0, c1, c0, 0 139 140#ifdef CONFIG_ARM_ERRATA_716044 141 mrc p15, 0, r0, c1, c0, 0 @ read system control register 142 orr r0, r0, #1 << 11 @ set bit #11 143 mcr p15, 0, r0, c1, c0, 0 @ write system control register 144#endif 145 146#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072)) 147 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 148 orr r0, r0, #1 << 4 @ set bit #4 149 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 150#endif 151 152#ifdef CONFIG_ARM_ERRATA_743622 153 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 154 orr r0, r0, #1 << 6 @ set bit #6 155 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 156#endif 157 158#ifdef CONFIG_ARM_ERRATA_751472 159 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 160 orr r0, r0, #1 << 11 @ set bit #11 161 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 162#endif 163#ifdef CONFIG_ARM_ERRATA_761320 164 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 165 orr r0, r0, #1 << 21 @ set bit #21 166 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 167#endif 168 169 mov r5, lr @ Store my Caller 170 mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR) 171 mov r3, r1, lsr #20 @ get variant field 172 and r3, r3, #0xf @ r3 has CPU variant 173 and r4, r1, #0xf @ r4 has CPU revision 174 mov r2, r3, lsl #4 @ shift variant field for combined value 175 orr r2, r4, r2 @ r2 has combined CPU variant + revision 176 177#ifdef CONFIG_ARM_ERRATA_798870 178 cmp r2, #0x30 @ Applies to lower than R3p0 179 bge skip_errata_798870 @ skip if not affected rev 180 cmp r2, #0x20 @ Applies to including and above R2p0 181 blt skip_errata_798870 @ skip if not affected rev 182 183 mrc p15, 1, r0, c15, c0, 0 @ read l2 aux ctrl reg 184 orr r0, r0, #1 << 7 @ Enable hazard-detect timeout 185 push {r1-r5} @ Save the cpu info registers 186 bl v7_arch_cp15_set_l2aux_ctrl 187 isb @ Recommended ISB after l2actlr update 188 pop {r1-r5} @ Restore the cpu info - fall through 189skip_errata_798870: 190#endif 191 192#ifdef CONFIG_ARM_ERRATA_454179 193 cmp r2, #0x21 @ Only on < r2p1 194 bge skip_errata_454179 195 196 mrc p15, 0, r0, c1, c0, 1 @ Read ACR 197 orr r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits 198 push {r1-r5} @ Save the cpu info registers 199 bl v7_arch_cp15_set_acr 200 pop {r1-r5} @ Restore the cpu info - fall through 201 202skip_errata_454179: 203#endif 204 205#ifdef CONFIG_ARM_ERRATA_430973 206 cmp r2, #0x21 @ Only on < r2p1 207 bge skip_errata_430973 208 209 mrc p15, 0, r0, c1, c0, 1 @ Read ACR 210 orr r0, r0, #(0x1 << 6) @ Set IBE bit 211 push {r1-r5} @ Save the cpu info registers 212 bl v7_arch_cp15_set_acr 213 pop {r1-r5} @ Restore the cpu info - fall through 214 215skip_errata_430973: 216#endif 217 218 mov pc, r5 @ back to my caller 219ENDPROC(cpu_init_cp15) 220 221#ifndef CONFIG_SKIP_LOWLEVEL_INIT 222/************************************************************************* 223 * 224 * CPU_init_critical registers 225 * 226 * setup important registers 227 * setup memory timing 228 * 229 *************************************************************************/ 230ENTRY(cpu_init_crit) 231 /* 232 * Jump to board specific initialization... 233 * The Mask ROM will have already initialized 234 * basic memory. Go here to bump up clock rate and handle 235 * wake up conditions. 236 */ 237 b lowlevel_init @ go setup pll,mux,memory 238ENDPROC(cpu_init_crit) 239#endif 240