1/* 2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com> 12 * 13 * See file CREDITS for list of people who contributed to this 14 * project. 15 * 16 * This program is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation; either version 2 of 19 * the License, or (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 29 * MA 02111-1307 USA 30 */ 31 32#include <asm-offsets.h> 33#include <config.h> 34#include <version.h> 35#include <asm/system.h> 36#include <linux/linkage.h> 37 38.globl _start 39_start: b reset 40 ldr pc, _undefined_instruction 41 ldr pc, _software_interrupt 42 ldr pc, _prefetch_abort 43 ldr pc, _data_abort 44 ldr pc, _not_used 45 ldr pc, _irq 46 ldr pc, _fiq 47#ifdef CONFIG_SPL_BUILD 48_undefined_instruction: .word _undefined_instruction 49_software_interrupt: .word _software_interrupt 50_prefetch_abort: .word _prefetch_abort 51_data_abort: .word _data_abort 52_not_used: .word _not_used 53_irq: .word _irq 54_fiq: .word _fiq 55_pad: .word 0x12345678 /* now 16*4=64 */ 56#else 57_undefined_instruction: .word undefined_instruction 58_software_interrupt: .word software_interrupt 59_prefetch_abort: .word prefetch_abort 60_data_abort: .word data_abort 61_not_used: .word not_used 62_irq: .word irq 63_fiq: .word fiq 64_pad: .word 0x12345678 /* now 16*4=64 */ 65#endif /* CONFIG_SPL_BUILD */ 66 67.global _end_vect 68_end_vect: 69 70 .balignl 16,0xdeadbeef 71/************************************************************************* 72 * 73 * Startup Code (reset vector) 74 * 75 * do important init only if we don't start from memory! 76 * setup Memory and board specific bits prior to relocation. 77 * relocate armboot to ram 78 * setup stack 79 * 80 *************************************************************************/ 81 82.globl _TEXT_BASE 83_TEXT_BASE: 84#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) 85 .word CONFIG_SPL_TEXT_BASE 86#else 87 .word CONFIG_SYS_TEXT_BASE 88#endif 89 90/* 91 * These are defined in the board-specific linker script. 92 */ 93.globl _bss_start_ofs 94_bss_start_ofs: 95 .word __bss_start - _start 96 97.global _image_copy_end_ofs 98_image_copy_end_ofs: 99 .word __image_copy_end - _start 100 101.globl _bss_end_ofs 102_bss_end_ofs: 103 .word __bss_end - _start 104 105.globl _end_ofs 106_end_ofs: 107 .word _end - _start 108 109#ifdef CONFIG_USE_IRQ 110/* IRQ stack memory (calculated at run-time) */ 111.globl IRQ_STACK_START 112IRQ_STACK_START: 113 .word 0x0badc0de 114 115/* IRQ stack memory (calculated at run-time) */ 116.globl FIQ_STACK_START 117FIQ_STACK_START: 118 .word 0x0badc0de 119#endif 120 121/* IRQ stack memory (calculated at run-time) + 8 bytes */ 122.globl IRQ_STACK_START_IN 123IRQ_STACK_START_IN: 124 .word 0x0badc0de 125 126/* 127 * the actual reset code 128 */ 129 130reset: 131 bl save_boot_params 132 /* 133 * set the cpu to SVC32 mode 134 */ 135 mrs r0, cpsr 136 bic r0, r0, #0x1f 137 orr r0, r0, #0xd3 138 msr cpsr,r0 139 140/* 141 * Setup vector: 142 * (OMAP4 spl TEXT_BASE is not 32 byte aligned. 143 * Continue to use ROM code vector only in OMAP4 spl) 144 */ 145#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) 146 /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */ 147 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register 148 bic r0, #CR_V @ V = 0 149 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register 150 151 /* Set vector address in CP15 VBAR register */ 152 ldr r0, =_start 153 mcr p15, 0, r0, c12, c0, 0 @Set VBAR 154#endif 155 156 /* the mask ROM code should have PLL and others stable */ 157#ifndef CONFIG_SKIP_LOWLEVEL_INIT 158 bl cpu_init_cp15 159 bl cpu_init_crit 160#endif 161 162 bl _main 163 164/*------------------------------------------------------------------------------*/ 165 166#ifndef CONFIG_SPL_BUILD 167/* 168 * void relocate_code (addr_sp, gd, addr_moni) 169 * 170 * This "function" does not return, instead it continues in RAM 171 * after relocating the monitor code. 172 * 173 */ 174ENTRY(relocate_code) 175 mov r4, r0 /* save addr_sp */ 176 mov r5, r1 /* save addr of gd */ 177 mov r6, r2 /* save addr of destination */ 178 179 adr r0, _start 180 cmp r0, r6 181 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ 182 beq relocate_done /* skip relocation */ 183 mov r1, r6 /* r1 <- scratch for copy_loop */ 184 ldr r3, _image_copy_end_ofs 185 add r2, r0, r3 /* r2 <- source end address */ 186 187copy_loop: 188 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 189 stmia r1!, {r9-r10} /* copy to target address [r1] */ 190 cmp r0, r2 /* until source end address [r2] */ 191 blo copy_loop 192 193 /* 194 * fix .rel.dyn relocations 195 */ 196 ldr r0, _TEXT_BASE /* r0 <- Text base */ 197 sub r9, r6, r0 /* r9 <- relocation offset */ 198 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 199 add r10, r10, r0 /* r10 <- sym table in FLASH */ 200 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 201 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 202 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 203 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 204fixloop: 205 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 206 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 207 ldr r1, [r2, #4] 208 and r7, r1, #0xff 209 cmp r7, #23 /* relative fixup? */ 210 beq fixrel 211 cmp r7, #2 /* absolute fixup? */ 212 beq fixabs 213 /* ignore unknown type of fixup */ 214 b fixnext 215fixabs: 216 /* absolute fix: set location to (offset) symbol value */ 217 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 218 add r1, r10, r1 /* r1 <- address of symbol in table */ 219 ldr r1, [r1, #4] /* r1 <- symbol value */ 220 add r1, r1, r9 /* r1 <- relocated sym addr */ 221 b fixnext 222fixrel: 223 /* relative fix: increase location by offset */ 224 ldr r1, [r0] 225 add r1, r1, r9 226fixnext: 227 str r1, [r0] 228 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 229 cmp r2, r3 230 blo fixloop 231 232relocate_done: 233 234 bx lr 235 236_rel_dyn_start_ofs: 237 .word __rel_dyn_start - _start 238_rel_dyn_end_ofs: 239 .word __rel_dyn_end - _start 240_dynsym_start_ofs: 241 .word __dynsym_start - _start 242ENDPROC(relocate_code) 243 244#endif 245 246ENTRY(c_runtime_cpu_setup) 247/* 248 * If I-cache is enabled invalidate it 249 */ 250#ifndef CONFIG_SYS_ICACHE_OFF 251 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 252 mcr p15, 0, r0, c7, c10, 4 @ DSB 253 mcr p15, 0, r0, c7, c5, 4 @ ISB 254#endif 255/* 256 * Move vector table 257 */ 258#if !defined(CONFIG_TEGRA) 259 /* Set vector address in CP15 VBAR register */ 260 ldr r0, =_start 261 mcr p15, 0, r0, c12, c0, 0 @Set VBAR 262#endif /* !Tegra */ 263 264 bx lr 265 266ENDPROC(c_runtime_cpu_setup) 267 268/************************************************************************* 269 * 270 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) 271 * __attribute__((weak)); 272 * 273 * Stack pointer is not yet initialized at this moment 274 * Don't save anything to stack even if compiled with -O0 275 * 276 *************************************************************************/ 277ENTRY(save_boot_params) 278 bx lr @ back to my caller 279ENDPROC(save_boot_params) 280 .weak save_boot_params 281 282/************************************************************************* 283 * 284 * cpu_init_cp15 285 * 286 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless 287 * CONFIG_SYS_ICACHE_OFF is defined. 288 * 289 *************************************************************************/ 290ENTRY(cpu_init_cp15) 291 /* 292 * Invalidate L1 I/D 293 */ 294 mov r0, #0 @ set up for MCR 295 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs 296 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 297 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array 298 mcr p15, 0, r0, c7, c10, 4 @ DSB 299 mcr p15, 0, r0, c7, c5, 4 @ ISB 300 301 /* 302 * disable MMU stuff and caches 303 */ 304 mrc p15, 0, r0, c1, c0, 0 305 bic r0, r0, #0x00002000 @ clear bits 13 (--V-) 306 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) 307 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align 308 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB 309#ifdef CONFIG_SYS_ICACHE_OFF 310 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache 311#else 312 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache 313#endif 314 mcr p15, 0, r0, c1, c0, 0 315 316#ifdef CONFIG_ARM_ERRATA_716044 317 mrc p15, 0, r0, c1, c0, 0 @ read system control register 318 orr r0, r0, #1 << 11 @ set bit #11 319 mcr p15, 0, r0, c1, c0, 0 @ write system control register 320#endif 321 322#ifdef CONFIG_ARM_ERRATA_742230 323 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 324 orr r0, r0, #1 << 4 @ set bit #4 325 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 326#endif 327 328#ifdef CONFIG_ARM_ERRATA_743622 329 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 330 orr r0, r0, #1 << 6 @ set bit #6 331 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 332#endif 333 334#ifdef CONFIG_ARM_ERRATA_751472 335 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 336 orr r0, r0, #1 << 11 @ set bit #11 337 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 338#endif 339 340 mov pc, lr @ back to my caller 341ENDPROC(cpu_init_cp15) 342 343#ifndef CONFIG_SKIP_LOWLEVEL_INIT 344/************************************************************************* 345 * 346 * CPU_init_critical registers 347 * 348 * setup important registers 349 * setup memory timing 350 * 351 *************************************************************************/ 352ENTRY(cpu_init_crit) 353 /* 354 * Jump to board specific initialization... 355 * The Mask ROM will have already initialized 356 * basic memory. Go here to bump up clock rate and handle 357 * wake up conditions. 358 */ 359 b lowlevel_init @ go setup pll,mux,memory 360ENDPROC(cpu_init_crit) 361#endif 362 363#ifndef CONFIG_SPL_BUILD 364/* 365 ************************************************************************* 366 * 367 * Interrupt handling 368 * 369 ************************************************************************* 370 */ 371@ 372@ IRQ stack frame. 373@ 374#define S_FRAME_SIZE 72 375 376#define S_OLD_R0 68 377#define S_PSR 64 378#define S_PC 60 379#define S_LR 56 380#define S_SP 52 381 382#define S_IP 48 383#define S_FP 44 384#define S_R10 40 385#define S_R9 36 386#define S_R8 32 387#define S_R7 28 388#define S_R6 24 389#define S_R5 20 390#define S_R4 16 391#define S_R3 12 392#define S_R2 8 393#define S_R1 4 394#define S_R0 0 395 396#define MODE_SVC 0x13 397#define I_BIT 0x80 398 399/* 400 * use bad_save_user_regs for abort/prefetch/undef/swi ... 401 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 402 */ 403 404 .macro bad_save_user_regs 405 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current 406 @ user stack 407 stmia sp, {r0 - r12} @ Save user registers (now in 408 @ svc mode) r0-r12 409 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort 410 @ stack 411 ldmia r2, {r2 - r3} @ get values for "aborted" pc 412 @ and cpsr (into parm regs) 413 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 414 415 add r5, sp, #S_SP 416 mov r1, lr 417 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 418 mov r0, sp @ save current stack into r0 419 @ (param register) 420 .endm 421 422 .macro irq_save_user_regs 423 sub sp, sp, #S_FRAME_SIZE 424 stmia sp, {r0 - r12} @ Calling r0-r12 425 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !! 426 @ a reserved stack spot would 427 @ be good. 428 stmdb r8, {sp, lr}^ @ Calling SP, LR 429 str lr, [r8, #0] @ Save calling PC 430 mrs r6, spsr 431 str r6, [r8, #4] @ Save CPSR 432 str r0, [r8, #8] @ Save OLD_R0 433 mov r0, sp 434 .endm 435 436 .macro irq_restore_user_regs 437 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 438 mov r0, r0 439 ldr lr, [sp, #S_PC] @ Get PC 440 add sp, sp, #S_FRAME_SIZE 441 subs pc, lr, #4 @ return & move spsr_svc into 442 @ cpsr 443 .endm 444 445 .macro get_bad_stack 446 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter 447 @ in banked mode) 448 449 str lr, [r13] @ save caller lr in position 0 450 @ of saved stack 451 mrs lr, spsr @ get the spsr 452 str lr, [r13, #4] @ save spsr in position 1 of 453 @ saved stack 454 455 mov r13, #MODE_SVC @ prepare SVC-Mode 456 @ msr spsr_c, r13 457 msr spsr, r13 @ switch modes, make sure 458 @ moves will execute 459 mov lr, pc @ capture return pc 460 movs pc, lr @ jump to next instruction & 461 @ switch modes. 462 .endm 463 464 .macro get_bad_stack_swi 465 sub r13, r13, #4 @ space on current stack for 466 @ scratch reg. 467 str r0, [r13] @ save R0's value. 468 ldr r0, IRQ_STACK_START_IN @ get data regions start 469 @ spots for abort stack 470 str lr, [r0] @ save caller lr in position 0 471 @ of saved stack 472 mrs r0, spsr @ get the spsr 473 str lr, [r0, #4] @ save spsr in position 1 of 474 @ saved stack 475 ldr r0, [r13] @ restore r0 476 add r13, r13, #4 @ pop stack entry 477 .endm 478 479 .macro get_irq_stack @ setup IRQ stack 480 ldr sp, IRQ_STACK_START 481 .endm 482 483 .macro get_fiq_stack @ setup FIQ stack 484 ldr sp, FIQ_STACK_START 485 .endm 486 487/* 488 * exception handlers 489 */ 490 .align 5 491undefined_instruction: 492 get_bad_stack 493 bad_save_user_regs 494 bl do_undefined_instruction 495 496 .align 5 497software_interrupt: 498 get_bad_stack_swi 499 bad_save_user_regs 500 bl do_software_interrupt 501 502 .align 5 503prefetch_abort: 504 get_bad_stack 505 bad_save_user_regs 506 bl do_prefetch_abort 507 508 .align 5 509data_abort: 510 get_bad_stack 511 bad_save_user_regs 512 bl do_data_abort 513 514 .align 5 515not_used: 516 get_bad_stack 517 bad_save_user_regs 518 bl do_not_used 519 520#ifdef CONFIG_USE_IRQ 521 522 .align 5 523irq: 524 get_irq_stack 525 irq_save_user_regs 526 bl do_irq 527 irq_restore_user_regs 528 529 .align 5 530fiq: 531 get_fiq_stack 532 /* someone ought to write a more effective fiq_save_user_regs */ 533 irq_save_user_regs 534 bl do_fiq 535 irq_restore_user_regs 536 537#else 538 539 .align 5 540irq: 541 get_bad_stack 542 bad_save_user_regs 543 bl do_irq 544 545 .align 5 546fiq: 547 get_bad_stack 548 bad_save_user_regs 549 bl do_fiq 550 551#endif /* CONFIG_USE_IRQ */ 552#endif /* CONFIG_SPL_BUILD */ 553