1/* 2 * code for switching cores into non-secure state and into HYP mode 3 * 4 * Copyright (c) 2013 Andre Przywara <andre.przywara@linaro.org> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9#include <config.h> 10#include <linux/linkage.h> 11#include <asm/gic.h> 12#include <asm/armv7.h> 13 14.arch_extension sec 15.arch_extension virt 16 17 .align 5 18/* the vector table for secure state and HYP mode */ 19_monitor_vectors: 20 .word 0 /* reset */ 21 .word 0 /* undef */ 22 adr pc, _secure_monitor 23 .word 0 24 .word 0 25 adr pc, _hyp_trap 26 .word 0 27 .word 0 28 29/* 30 * secure monitor handler 31 * U-boot calls this "software interrupt" in start.S 32 * This is executed on a "smc" instruction, we use a "smc #0" to switch 33 * to non-secure state. 34 * We use only r0 and r1 here, due to constraints in the caller. 35 */ 36_secure_monitor: 37 mrc p15, 0, r1, c1, c1, 0 @ read SCR 38 bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits 39 orr r1, r1, #0x31 @ enable NS, AW, FW bits 40 41 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 42 and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits 43 cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT) 44#ifdef CONFIG_ARMV7_VIRT 45 orreq r1, r1, #0x100 @ allow HVC instruction 46#endif 47 48 mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set) 49 isb 50 51#ifdef CONFIG_ARMV7_VIRT 52 mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value 53 mcreq p15, 4, r0, c12, c0, 0 @ write HVBAR 54#endif 55 bne 1f 56 57 @ Reset CNTVOFF to 0 before leaving monitor mode 58 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 59 ands r0, r0, #CPUID_ARM_GENTIMER_MASK @ test arch timer bits 60 movne r0, #0 61 mcrrne p15, 4, r0, r0, c14 @ Reset CNTVOFF to zero 621: 63 movs pc, lr @ return to non-secure SVC 64 65_hyp_trap: 66 mrs lr, elr_hyp @ for older asm: .byte 0x00, 0xe3, 0x0e, 0xe1 67 mov pc, lr @ do no switch modes, but 68 @ return to caller 69 70/* 71 * Secondary CPUs start here and call the code for the core specific parts 72 * of the non-secure and HYP mode transition. The GIC distributor specific 73 * code has already been executed by a C function before. 74 * Then they go back to wfi and wait to be woken up by the kernel again. 75 */ 76ENTRY(_smp_pen) 77 mrs r0, cpsr 78 orr r0, r0, #0xc0 79 msr cpsr, r0 @ disable interrupts 80 ldr r1, =_start 81 mcr p15, 0, r1, c12, c0, 0 @ set VBAR 82 83 bl _nonsec_init 84 mov r12, r0 @ save GICC address 85#ifdef CONFIG_ARMV7_VIRT 86 bl _switch_to_hyp 87#endif 88 89 ldr r1, [r12, #GICC_IAR] @ acknowledge IPI 90 str r1, [r12, #GICC_EOIR] @ signal end of interrupt 91 92 adr r0, _smp_pen @ do not use this address again 93 b smp_waitloop @ wait for IPIs, board specific 94ENDPROC(_smp_pen) 95 96/* 97 * Switch a core to non-secure state. 98 * 99 * 1. initialize the GIC per-core interface 100 * 2. allow coprocessor access in non-secure modes 101 * 3. switch the cpu mode (by calling "smc #0") 102 * 103 * Called from smp_pen by secondary cores and directly by the BSP. 104 * Do not assume that the stack is available and only use registers 105 * r0-r3 and r12. 106 * 107 * PERIPHBASE is used to get the GIC address. This could be 40 bits long, 108 * though, but we check this in C before calling this function. 109 */ 110ENTRY(_nonsec_init) 111#ifdef CONFIG_ARM_GIC_BASE_ADDRESS 112 ldr r2, =CONFIG_ARM_GIC_BASE_ADDRESS 113#else 114 mrc p15, 4, r2, c15, c0, 0 @ read CBAR 115 bfc r2, #0, #15 @ clear reserved bits 116#endif 117 add r3, r2, #GIC_DIST_OFFSET @ GIC dist i/f offset 118 mvn r1, #0 @ all bits to 1 119 str r1, [r3, #GICD_IGROUPRn] @ allow private interrupts 120 121 mrc p15, 0, r0, c0, c0, 0 @ read MIDR 122 ldr r1, =MIDR_PRIMARY_PART_MASK 123 and r0, r0, r1 @ mask out variant and revision 124 125 ldr r1, =MIDR_CORTEX_A7_R0P0 & MIDR_PRIMARY_PART_MASK 126 cmp r0, r1 @ check for Cortex-A7 127 128 ldr r1, =MIDR_CORTEX_A15_R0P0 & MIDR_PRIMARY_PART_MASK 129 cmpne r0, r1 @ check for Cortex-A15 130 131 movne r1, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9 132 moveq r1, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7 133 add r3, r2, r1 @ r3 = GIC CPU i/f addr 134 135 mov r1, #1 @ set GICC_CTLR[enable] 136 str r1, [r3, #GICC_CTLR] @ and clear all other bits 137 mov r1, #0xff 138 str r1, [r3, #GICC_PMR] @ set priority mask register 139 140 movw r1, #0x3fff 141 movt r1, #0x0006 142 mcr p15, 0, r1, c1, c1, 2 @ NSACR = all copros to non-sec 143 144/* The CNTFRQ register of the generic timer needs to be 145 * programmed in secure state. Some primary bootloaders / firmware 146 * omit this, so if the frequency is provided in the configuration, 147 * we do this here instead. 148 * But first check if we have the generic timer. 149 */ 150#ifdef CONFIG_SYS_CLK_FREQ 151 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 152 and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits 153 cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT) 154 ldreq r1, =CONFIG_SYS_CLK_FREQ 155 mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ 156#endif 157 158 adr r1, _monitor_vectors 159 mcr p15, 0, r1, c12, c0, 1 @ set MVBAR to secure vectors 160 161 mrc p15, 0, ip, c12, c0, 0 @ save secure copy of VBAR 162 163 isb 164 smc #0 @ call into MONITOR mode 165 166 mcr p15, 0, ip, c12, c0, 0 @ write non-secure copy of VBAR 167 168 mov r1, #1 169 str r1, [r3, #GICC_CTLR] @ enable non-secure CPU i/f 170 add r2, r2, #GIC_DIST_OFFSET 171 str r1, [r2, #GICD_CTLR] @ allow private interrupts 172 173 mov r0, r3 @ return GICC address 174 175 bx lr 176ENDPROC(_nonsec_init) 177 178#ifdef CONFIG_SMP_PEN_ADDR 179/* void __weak smp_waitloop(unsigned previous_address); */ 180ENTRY(smp_waitloop) 181 wfi 182 ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address 183 ldr r1, [r1] 184 cmp r0, r1 @ make sure we dont execute this code 185 beq smp_waitloop @ again (due to a spurious wakeup) 186 mov pc, r1 187ENDPROC(smp_waitloop) 188.weak smp_waitloop 189#endif 190 191ENTRY(_switch_to_hyp) 192 mov r0, lr 193 mov r1, sp @ save SVC copy of LR and SP 194 isb 195 hvc #0 @ for older asm: .byte 0x70, 0x00, 0x40, 0xe1 196 mov sp, r1 197 mov lr, r0 @ restore SVC copy of LR and SP 198 199 bx lr 200ENDPROC(_switch_to_hyp) 201