1*989ce049SDarwin Rambo /* 2*989ce049SDarwin Rambo * Copyright 2013 Broadcom Corporation. 3*989ce049SDarwin Rambo * 4*989ce049SDarwin Rambo * SPDX-License-Identifier: GPL-2.0+ 5*989ce049SDarwin Rambo */ 6*989ce049SDarwin Rambo 7*989ce049SDarwin Rambo #include <common.h> 8*989ce049SDarwin Rambo #include <asm/io.h> 9*989ce049SDarwin Rambo #include <asm/arch/sysmap.h> 10*989ce049SDarwin Rambo 11*989ce049SDarwin Rambo #define EN_MASK 0x08000000 /* Enable timer */ 12*989ce049SDarwin Rambo #define SRSTEN_MASK 0x04000000 /* Enable soft reset */ 13*989ce049SDarwin Rambo #define CLKS_SHIFT 20 /* Clock period shift */ 14*989ce049SDarwin Rambo #define LD_SHIFT 0 /* Reload value shift */ 15*989ce049SDarwin Rambo reset_cpu(ulong ignored)16*989ce049SDarwin Rambovoid reset_cpu(ulong ignored) 17*989ce049SDarwin Rambo { 18*989ce049SDarwin Rambo /* 19*989ce049SDarwin Rambo * Set WD enable, RST enable, 20*989ce049SDarwin Rambo * 3.9 msec clock period (8), reload value (8*3.9ms) 21*989ce049SDarwin Rambo */ 22*989ce049SDarwin Rambo u32 reg = EN_MASK + SRSTEN_MASK + (8 << CLKS_SHIFT) + (8 << LD_SHIFT); 23*989ce049SDarwin Rambo writel(reg, SECWD2_BASE_ADDR); 24*989ce049SDarwin Rambo 25*989ce049SDarwin Rambo while (1) 26*989ce049SDarwin Rambo ; /* loop forever till reset */ 27*989ce049SDarwin Rambo } 28