1ea624e19SHans de Goedeif CPU_V7 2ea624e19SHans de Goede 3ea624e19SHans de Goedeconfig CPU_V7_HAS_NONSEC 4ea624e19SHans de Goede bool 5ea624e19SHans de Goede 6ea624e19SHans de Goedeconfig CPU_V7_HAS_VIRT 7ea624e19SHans de Goede bool 8ea624e19SHans de Goede 9217f92bbSMasahiro Yamadaconfig ARCH_SUPPORT_PSCI 10217f92bbSMasahiro Yamada bool 11217f92bbSMasahiro Yamada 12ea624e19SHans de Goedeconfig ARMV7_NONSEC 13ab65006bSMasahiro Yamada bool "Enable support for booting in non-secure mode" if EXPERT 14ea624e19SHans de Goede depends on CPU_V7_HAS_NONSEC 15ea624e19SHans de Goede default y 16ea624e19SHans de Goede ---help--- 17ea624e19SHans de Goede Say Y here to enable support for booting in non-secure / SVC mode. 18ea624e19SHans de Goede 198bc347e2SHans de Goedeconfig ARMV7_BOOT_SEC_DEFAULT 20ab65006bSMasahiro Yamada bool "Boot in secure mode by default" if EXPERT 218bc347e2SHans de Goede depends on ARMV7_NONSEC 22a8f2d019SJan Kiszka default y if TEGRA 238bc347e2SHans de Goede ---help--- 248bc347e2SHans de Goede Say Y here to boot in secure mode by default even if non-secure mode 258bc347e2SHans de Goede is supported. This option is useful to boot kernels which do not 268bc347e2SHans de Goede suppport booting in non-secure mode. Only set this if you need it. 2762a3b7ddSRobert P. J. Day This can be overridden at run-time by setting the bootm_boot_mode env. 288bc347e2SHans de Goede variable to "sec" or "nonsec". 298bc347e2SHans de Goede 30ea624e19SHans de Goedeconfig ARMV7_VIRT 31ab65006bSMasahiro Yamada bool "Enable support for hardware virtualization" if EXPERT 32ea624e19SHans de Goede depends on CPU_V7_HAS_VIRT && ARMV7_NONSEC 33ea624e19SHans de Goede default y 34ea624e19SHans de Goede ---help--- 35ea624e19SHans de Goede Say Y here to boot in hypervisor (HYP) mode when booting non-secure. 36ea624e19SHans de Goede 37217f92bbSMasahiro Yamadaconfig ARMV7_PSCI 38217f92bbSMasahiro Yamada bool "Enable PSCI support" if EXPERT 39217f92bbSMasahiro Yamada depends on ARMV7_NONSEC && ARCH_SUPPORT_PSCI 40217f92bbSMasahiro Yamada default y 41217f92bbSMasahiro Yamada help 42217f92bbSMasahiro Yamada Say Y here to enable PSCI support. 43217f92bbSMasahiro Yamada 44*15446988SMasahiro Yamadaconfig ARMV7_PSCI_NR_CPUS 45*15446988SMasahiro Yamada int "Maximum supported CPUs for PSCI" 46*15446988SMasahiro Yamada depends on ARMV7_NONSEC 47*15446988SMasahiro Yamada default 4 48*15446988SMasahiro Yamada help 49*15446988SMasahiro Yamada The maximum number of CPUs supported in the PSCI firmware. 50*15446988SMasahiro Yamada It is no problem to set a larger value than the number of 51*15446988SMasahiro Yamada CPUs in the actual hardware implementation. 52*15446988SMasahiro Yamada 53d990f5c8SAlexander Grafconfig ARMV7_LPAE 54ab65006bSMasahiro Yamada bool "Use LPAE page table format" if EXPERT 55d990f5c8SAlexander Graf depends on CPU_V7 56d990f5c8SAlexander Graf default n 57d990f5c8SAlexander Graf ---help--- 58d990f5c8SAlexander Graf Say Y here to use the long descriptor page table format. This is 59d990f5c8SAlexander Graf required if U-Boot runs in HYP mode. 60d990f5c8SAlexander Graf 61ea624e19SHans de Goedeendif 62