1/* 2 * armboot - Startup Code for ARM926EJS CPU-core 3 * 4 * Copyright (c) 2003 Texas Instruments 5 * 6 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ 7 * 8 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 9 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 10 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 12 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 13 * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net> 14 * 15 * See file CREDITS for list of people who contributed to this 16 * project. 17 * 18 * This program is free software; you can redistribute it and/or 19 * modify it under the terms of the GNU General Public License as 20 * published by the Free Software Foundation; either version 2 of 21 * the License, or (at your option) any later version. 22 * 23 * This program is distributed in the hope that it will be useful, 24 * but WITHOUT ANY WARRANTY; without even the implied warranty of 25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 * GNU General Public License for more details. 27 * 28 * You should have received a copy of the GNU General Public License 29 * along with this program; if not, write to the Free Software 30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 31 * MA 02111-1307 USA 32 */ 33 34#include <asm-offsets.h> 35#include <config.h> 36#include <common.h> 37#include <version.h> 38 39/* 40 ************************************************************************* 41 * 42 * Jump vector table as in table 3.1 in [1] 43 * 44 ************************************************************************* 45 */ 46 47 48#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG 49.globl _start 50_start: 51.globl _NOR_BOOT_CFG 52_NOR_BOOT_CFG: 53 .word CONFIG_SYS_DV_NOR_BOOT_CFG 54 b reset 55#else 56.globl _start 57_start: 58 b reset 59#endif 60#ifdef CONFIG_SPL_BUILD 61/* No exception handlers in preloader */ 62 ldr pc, _hang 63 ldr pc, _hang 64 ldr pc, _hang 65 ldr pc, _hang 66 ldr pc, _hang 67 ldr pc, _hang 68 ldr pc, _hang 69 70_hang: 71 .word do_hang 72/* pad to 64 byte boundary */ 73 .word 0x12345678 74 .word 0x12345678 75 .word 0x12345678 76 .word 0x12345678 77 .word 0x12345678 78 .word 0x12345678 79 .word 0x12345678 80#else 81 ldr pc, _undefined_instruction 82 ldr pc, _software_interrupt 83 ldr pc, _prefetch_abort 84 ldr pc, _data_abort 85 ldr pc, _not_used 86 ldr pc, _irq 87 ldr pc, _fiq 88 89_undefined_instruction: 90 .word undefined_instruction 91_software_interrupt: 92 .word software_interrupt 93_prefetch_abort: 94 .word prefetch_abort 95_data_abort: 96 .word data_abort 97_not_used: 98 .word not_used 99_irq: 100 .word irq 101_fiq: 102 .word fiq 103 104#endif /* CONFIG_SPL_BUILD */ 105 .balignl 16,0xdeadbeef 106 107 108/* 109 ************************************************************************* 110 * 111 * Startup Code (reset vector) 112 * 113 * do important init only if we don't start from memory! 114 * setup Memory and board specific bits prior to relocation. 115 * relocate armboot to ram 116 * setup stack 117 * 118 ************************************************************************* 119 */ 120 121.globl _TEXT_BASE 122_TEXT_BASE: 123#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) 124 .word CONFIG_SPL_TEXT_BASE 125#else 126 .word CONFIG_SYS_TEXT_BASE 127#endif 128 129/* 130 * These are defined in the board-specific linker script. 131 * Subtracting _start from them lets the linker put their 132 * relative position in the executable instead of leaving 133 * them null. 134 */ 135.globl _bss_start_ofs 136_bss_start_ofs: 137 .word __bss_start - _start 138 139.globl _bss_end_ofs 140_bss_end_ofs: 141 .word __bss_end - _start 142 143.globl _end_ofs 144_end_ofs: 145 .word _end - _start 146 147#ifdef CONFIG_USE_IRQ 148/* IRQ stack memory (calculated at run-time) */ 149.globl IRQ_STACK_START 150IRQ_STACK_START: 151 .word 0x0badc0de 152 153/* IRQ stack memory (calculated at run-time) */ 154.globl FIQ_STACK_START 155FIQ_STACK_START: 156 .word 0x0badc0de 157#endif 158 159/* IRQ stack memory (calculated at run-time) + 8 bytes */ 160.globl IRQ_STACK_START_IN 161IRQ_STACK_START_IN: 162 .word 0x0badc0de 163 164/* 165 * the actual reset code 166 */ 167 168reset: 169 /* 170 * set the cpu to SVC32 mode 171 */ 172 mrs r0,cpsr 173 bic r0,r0,#0x1f 174 orr r0,r0,#0xd3 175 msr cpsr,r0 176 177 /* 178 * we do sys-critical inits only at reboot, 179 * not when booting from ram! 180 */ 181#ifndef CONFIG_SKIP_LOWLEVEL_INIT 182 bl cpu_init_crit 183#endif 184 185 bl _main 186 187/*------------------------------------------------------------------------------*/ 188 189#ifndef CONFIG_SPL_BUILD 190/* 191 * void relocate_code(addr_moni) 192 * 193 * This function relocates the monitor code. 194 */ 195 .globl relocate_code 196relocate_code: 197 mov r6, r0 /* save addr of destination */ 198 199 adr r0, _start 200 subs r9, r6, r0 /* r9 <- relocation offset */ 201 beq relocate_done /* skip relocation */ 202 mov r1, r6 /* r1 <- scratch for copy loop */ 203 ldr r3, _image_copy_end_ofs 204 add r2, r0, r3 /* r2 <- source end address */ 205 206copy_loop: 207 ldmia r0!, {r10-r11} /* copy from source address [r0] */ 208 stmia r1!, {r10-r11} /* copy to target address [r1] */ 209 cmp r0, r2 /* until source end address [r2] */ 210 blo copy_loop 211 212 /* 213 * fix .rel.dyn relocations 214 */ 215 ldr r0, _TEXT_BASE /* r0 <- Text base */ 216 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 217 add r10, r10, r0 /* r10 <- sym table in FLASH */ 218 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 219 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 220 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 221 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 222fixloop: 223 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 224 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 225 ldr r1, [r2, #4] 226 and r7, r1, #0xff 227 cmp r7, #23 /* relative fixup? */ 228 beq fixrel 229 cmp r7, #2 /* absolute fixup? */ 230 beq fixabs 231 /* ignore unknown type of fixup */ 232 b fixnext 233fixabs: 234 /* absolute fix: set location to (offset) symbol value */ 235 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 236 add r1, r10, r1 /* r1 <- address of symbol in table */ 237 ldr r1, [r1, #4] /* r1 <- symbol value */ 238 add r1, r1, r9 /* r1 <- relocated sym addr */ 239 b fixnext 240fixrel: 241 /* relative fix: increase location by offset */ 242 ldr r1, [r0] 243 add r1, r1, r9 244fixnext: 245 str r1, [r0] 246 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 247 cmp r2, r3 248 blo fixloop 249 250relocate_done: 251 252 bx lr 253 254_image_copy_end_ofs: 255 .word __image_copy_end - _start 256_rel_dyn_start_ofs: 257 .word __rel_dyn_start - _start 258_rel_dyn_end_ofs: 259 .word __rel_dyn_end - _start 260_dynsym_start_ofs: 261 .word __dynsym_start - _start 262 263#endif 264 265 .globl c_runtime_cpu_setup 266c_runtime_cpu_setup: 267 268 bx lr 269 270/* 271 ************************************************************************* 272 * 273 * CPU_init_critical registers 274 * 275 * setup important registers 276 * setup memory timing 277 * 278 ************************************************************************* 279 */ 280#ifndef CONFIG_SKIP_LOWLEVEL_INIT 281cpu_init_crit: 282 /* 283 * flush D cache before disabling it 284 */ 285 mov r0, #0 286flush_dcache: 287 mrc p15, 0, r15, c7, c10, 3 288 bne flush_dcache 289 290 mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */ 291 mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */ 292 293 /* 294 * disable MMU and D cache 295 * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined 296 */ 297 mrc p15, 0, r0, c1, c0, 0 298 bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */ 299 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ 300#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH 301 orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */ 302#else 303 bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ 304#endif 305 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ 306#ifndef CONFIG_SYS_ICACHE_OFF 307 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ 308#endif 309 mcr p15, 0, r0, c1, c0, 0 310 311 /* 312 * Go setup Memory and board specific bits prior to relocation. 313 */ 314 mov ip, lr /* perserve link reg across call */ 315 bl lowlevel_init /* go setup pll,mux,memory */ 316 mov lr, ip /* restore link */ 317 mov pc, lr /* back to my caller */ 318#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 319 320#ifndef CONFIG_SPL_BUILD 321/* 322 ************************************************************************* 323 * 324 * Interrupt handling 325 * 326 ************************************************************************* 327 */ 328 329@ 330@ IRQ stack frame. 331@ 332#define S_FRAME_SIZE 72 333 334#define S_OLD_R0 68 335#define S_PSR 64 336#define S_PC 60 337#define S_LR 56 338#define S_SP 52 339 340#define S_IP 48 341#define S_FP 44 342#define S_R10 40 343#define S_R9 36 344#define S_R8 32 345#define S_R7 28 346#define S_R6 24 347#define S_R5 20 348#define S_R4 16 349#define S_R3 12 350#define S_R2 8 351#define S_R1 4 352#define S_R0 0 353 354#define MODE_SVC 0x13 355#define I_BIT 0x80 356 357/* 358 * use bad_save_user_regs for abort/prefetch/undef/swi ... 359 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 360 */ 361 362 .macro bad_save_user_regs 363 @ carve out a frame on current user stack 364 sub sp, sp, #S_FRAME_SIZE 365 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 366 ldr r2, IRQ_STACK_START_IN 367 @ get values for "aborted" pc and cpsr (into parm regs) 368 ldmia r2, {r2 - r3} 369 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 370 add r5, sp, #S_SP 371 mov r1, lr 372 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 373 mov r0, sp @ save current stack into r0 (param register) 374 .endm 375 376 .macro irq_save_user_regs 377 sub sp, sp, #S_FRAME_SIZE 378 stmia sp, {r0 - r12} @ Calling r0-r12 379 @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 380 add r8, sp, #S_PC 381 stmdb r8, {sp, lr}^ @ Calling SP, LR 382 str lr, [r8, #0] @ Save calling PC 383 mrs r6, spsr 384 str r6, [r8, #4] @ Save CPSR 385 str r0, [r8, #8] @ Save OLD_R0 386 mov r0, sp 387 .endm 388 389 .macro irq_restore_user_regs 390 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 391 mov r0, r0 392 ldr lr, [sp, #S_PC] @ Get PC 393 add sp, sp, #S_FRAME_SIZE 394 subs pc, lr, #4 @ return & move spsr_svc into cpsr 395 .endm 396 397 .macro get_bad_stack 398 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 399 400 str lr, [r13] @ save caller lr in position 0 of saved stack 401 mrs lr, spsr @ get the spsr 402 str lr, [r13, #4] @ save spsr in position 1 of saved stack 403 mov r13, #MODE_SVC @ prepare SVC-Mode 404 @ msr spsr_c, r13 405 msr spsr, r13 @ switch modes, make sure moves will execute 406 mov lr, pc @ capture return pc 407 movs pc, lr @ jump to next instruction & switch modes. 408 .endm 409 410 .macro get_irq_stack @ setup IRQ stack 411 ldr sp, IRQ_STACK_START 412 .endm 413 414 .macro get_fiq_stack @ setup FIQ stack 415 ldr sp, FIQ_STACK_START 416 .endm 417#endif /* CONFIG_SPL_BUILD */ 418 419/* 420 * exception handlers 421 */ 422#ifdef CONFIG_SPL_BUILD 423 .align 5 424do_hang: 425 ldr sp, _TEXT_BASE /* switch to abort stack */ 4261: 427 bl 1b /* hang and never return */ 428#else /* !CONFIG_SPL_BUILD */ 429 .align 5 430undefined_instruction: 431 get_bad_stack 432 bad_save_user_regs 433 bl do_undefined_instruction 434 435 .align 5 436software_interrupt: 437 get_bad_stack 438 bad_save_user_regs 439 bl do_software_interrupt 440 441 .align 5 442prefetch_abort: 443 get_bad_stack 444 bad_save_user_regs 445 bl do_prefetch_abort 446 447 .align 5 448data_abort: 449 get_bad_stack 450 bad_save_user_regs 451 bl do_data_abort 452 453 .align 5 454not_used: 455 get_bad_stack 456 bad_save_user_regs 457 bl do_not_used 458 459#ifdef CONFIG_USE_IRQ 460 461 .align 5 462irq: 463 get_irq_stack 464 irq_save_user_regs 465 bl do_irq 466 irq_restore_user_regs 467 468 .align 5 469fiq: 470 get_fiq_stack 471 /* someone ought to write a more effiction fiq_save_user_regs */ 472 irq_save_user_regs 473 bl do_fiq 474 irq_restore_user_regs 475 476#else 477 478 .align 5 479irq: 480 get_bad_stack 481 bad_save_user_regs 482 bl do_irq 483 484 .align 5 485fiq: 486 get_bad_stack 487 bad_save_user_regs 488 bl do_fiq 489 490#endif 491#endif /* CONFIG_SPL_BUILD */ 492