1/* 2 * armboot - Startup Code for ARM926EJS CPU-core 3 * 4 * Copyright (c) 2003 Texas Instruments 5 * 6 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ 7 * 8 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 9 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 10 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 12 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 13 * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net> 14 * 15 * See file CREDITS for list of people who contributed to this 16 * project. 17 * 18 * This program is free software; you can redistribute it and/or 19 * modify it under the terms of the GNU General Public License as 20 * published by the Free Software Foundation; either version 2 of 21 * the License, or (at your option) any later version. 22 * 23 * This program is distributed in the hope that it will be useful, 24 * but WITHOUT ANY WARRANTY; without even the implied warranty of 25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 * GNU General Public License for more details. 27 * 28 * You should have received a copy of the GNU General Public License 29 * along with this program; if not, write to the Free Software 30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 31 * MA 02111-1307 USA 32 */ 33 34#include <asm-offsets.h> 35#include <config.h> 36#include <common.h> 37#include <version.h> 38 39/* 40 ************************************************************************* 41 * 42 * Jump vector table as in table 3.1 in [1] 43 * 44 ************************************************************************* 45 */ 46 47 48#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG 49.globl _start 50_start: 51.globl _NOR_BOOT_CFG 52_NOR_BOOT_CFG: 53 .word CONFIG_SYS_DV_NOR_BOOT_CFG 54 b reset 55#else 56.globl _start 57_start: 58 b reset 59#endif 60#ifdef CONFIG_SPL_BUILD 61/* No exception handlers in preloader */ 62 ldr pc, _hang 63 ldr pc, _hang 64 ldr pc, _hang 65 ldr pc, _hang 66 ldr pc, _hang 67 ldr pc, _hang 68 ldr pc, _hang 69 70_hang: 71 .word do_hang 72/* pad to 64 byte boundary */ 73 .word 0x12345678 74 .word 0x12345678 75 .word 0x12345678 76 .word 0x12345678 77 .word 0x12345678 78 .word 0x12345678 79 .word 0x12345678 80#else 81 ldr pc, _undefined_instruction 82 ldr pc, _software_interrupt 83 ldr pc, _prefetch_abort 84 ldr pc, _data_abort 85 ldr pc, _not_used 86 ldr pc, _irq 87 ldr pc, _fiq 88 89_undefined_instruction: 90 .word undefined_instruction 91_software_interrupt: 92 .word software_interrupt 93_prefetch_abort: 94 .word prefetch_abort 95_data_abort: 96 .word data_abort 97_not_used: 98 .word not_used 99_irq: 100 .word irq 101_fiq: 102 .word fiq 103 104#endif /* CONFIG_SPL_BUILD */ 105 .balignl 16,0xdeadbeef 106 107 108/* 109 ************************************************************************* 110 * 111 * Startup Code (reset vector) 112 * 113 * do important init only if we don't start from memory! 114 * setup Memory and board specific bits prior to relocation. 115 * relocate armboot to ram 116 * setup stack 117 * 118 ************************************************************************* 119 */ 120 121.globl _TEXT_BASE 122_TEXT_BASE: 123#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) 124 .word CONFIG_SPL_TEXT_BASE 125#else 126 .word CONFIG_SYS_TEXT_BASE 127#endif 128 129/* 130 * These are defined in the board-specific linker script. 131 * Subtracting _start from them lets the linker put their 132 * relative position in the executable instead of leaving 133 * them null. 134 */ 135.globl _bss_start_ofs 136_bss_start_ofs: 137 .word __bss_start - _start 138 139.globl _image_copy_end_ofs 140_image_copy_end_ofs: 141 .word __image_copy_end - _start 142 143.globl _bss_end_ofs 144_bss_end_ofs: 145 .word __bss_end - _start 146 147.globl _end_ofs 148_end_ofs: 149 .word _end - _start 150 151#ifdef CONFIG_USE_IRQ 152/* IRQ stack memory (calculated at run-time) */ 153.globl IRQ_STACK_START 154IRQ_STACK_START: 155 .word 0x0badc0de 156 157/* IRQ stack memory (calculated at run-time) */ 158.globl FIQ_STACK_START 159FIQ_STACK_START: 160 .word 0x0badc0de 161#endif 162 163/* IRQ stack memory (calculated at run-time) + 8 bytes */ 164.globl IRQ_STACK_START_IN 165IRQ_STACK_START_IN: 166 .word 0x0badc0de 167 168/* 169 * the actual reset code 170 */ 171 172reset: 173 /* 174 * set the cpu to SVC32 mode 175 */ 176 mrs r0,cpsr 177 bic r0,r0,#0x1f 178 orr r0,r0,#0xd3 179 msr cpsr,r0 180 181 /* 182 * we do sys-critical inits only at reboot, 183 * not when booting from ram! 184 */ 185#ifndef CONFIG_SKIP_LOWLEVEL_INIT 186 bl cpu_init_crit 187#endif 188 189 bl _main 190 191/*------------------------------------------------------------------------------*/ 192 193/* 194 * void relocate_code (addr_sp, gd, addr_moni) 195 * 196 * This function relocates the monitor code. 197 */ 198 .globl relocate_code 199relocate_code: 200 mov r4, r0 /* save addr_sp */ 201 mov r5, r1 /* save addr of gd */ 202 mov r6, r2 /* save addr of destination */ 203 204 adr r0, _start 205 subs r9, r6, r0 /* r9 <- relocation offset */ 206 beq relocate_done /* skip relocation */ 207 mov r1, r6 /* r1 <- scratch for copy loop */ 208 ldr r3, _image_copy_end_ofs 209 add r2, r0, r3 /* r2 <- source end address */ 210 211copy_loop: 212 ldmia r0!, {r10-r11} /* copy from source address [r0] */ 213 stmia r1!, {r10-r11} /* copy to target address [r1] */ 214 cmp r0, r2 /* until source end address [r2] */ 215 blo copy_loop 216 217#ifndef CONFIG_SPL_BUILD 218 /* 219 * fix .rel.dyn relocations 220 */ 221 ldr r0, _TEXT_BASE /* r0 <- Text base */ 222 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 223 add r10, r10, r0 /* r10 <- sym table in FLASH */ 224 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 225 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 226 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 227 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 228fixloop: 229 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 230 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 231 ldr r1, [r2, #4] 232 and r7, r1, #0xff 233 cmp r7, #23 /* relative fixup? */ 234 beq fixrel 235 cmp r7, #2 /* absolute fixup? */ 236 beq fixabs 237 /* ignore unknown type of fixup */ 238 b fixnext 239fixabs: 240 /* absolute fix: set location to (offset) symbol value */ 241 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 242 add r1, r10, r1 /* r1 <- address of symbol in table */ 243 ldr r1, [r1, #4] /* r1 <- symbol value */ 244 add r1, r1, r9 /* r1 <- relocated sym addr */ 245 b fixnext 246fixrel: 247 /* relative fix: increase location by offset */ 248 ldr r1, [r0] 249 add r1, r1, r9 250fixnext: 251 str r1, [r0] 252 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 253 cmp r2, r3 254 blo fixloop 255#endif 256 257relocate_done: 258 259 bx lr 260 261#ifndef CONFIG_SPL_BUILD 262 263_rel_dyn_start_ofs: 264 .word __rel_dyn_start - _start 265_rel_dyn_end_ofs: 266 .word __rel_dyn_end - _start 267_dynsym_start_ofs: 268 .word __dynsym_start - _start 269 270#endif 271 272 .globl c_runtime_cpu_setup 273c_runtime_cpu_setup: 274 275 bx lr 276 277/* 278 ************************************************************************* 279 * 280 * CPU_init_critical registers 281 * 282 * setup important registers 283 * setup memory timing 284 * 285 ************************************************************************* 286 */ 287#ifndef CONFIG_SKIP_LOWLEVEL_INIT 288cpu_init_crit: 289 /* 290 * flush D cache before disabling it 291 */ 292 mov r0, #0 293flush_dcache: 294 mrc p15, 0, r15, c7, c10, 3 295 bne flush_dcache 296 297 mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */ 298 mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */ 299 300 /* 301 * disable MMU and D cache 302 * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined 303 */ 304 mrc p15, 0, r0, c1, c0, 0 305 bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */ 306 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ 307#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH 308 orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */ 309#else 310 bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ 311#endif 312 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ 313#ifndef CONFIG_SYS_ICACHE_OFF 314 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ 315#endif 316 mcr p15, 0, r0, c1, c0, 0 317 318 /* 319 * Go setup Memory and board specific bits prior to relocation. 320 */ 321 mov ip, lr /* perserve link reg across call */ 322 bl lowlevel_init /* go setup pll,mux,memory */ 323 mov lr, ip /* restore link */ 324 mov pc, lr /* back to my caller */ 325#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 326 327#ifndef CONFIG_SPL_BUILD 328/* 329 ************************************************************************* 330 * 331 * Interrupt handling 332 * 333 ************************************************************************* 334 */ 335 336@ 337@ IRQ stack frame. 338@ 339#define S_FRAME_SIZE 72 340 341#define S_OLD_R0 68 342#define S_PSR 64 343#define S_PC 60 344#define S_LR 56 345#define S_SP 52 346 347#define S_IP 48 348#define S_FP 44 349#define S_R10 40 350#define S_R9 36 351#define S_R8 32 352#define S_R7 28 353#define S_R6 24 354#define S_R5 20 355#define S_R4 16 356#define S_R3 12 357#define S_R2 8 358#define S_R1 4 359#define S_R0 0 360 361#define MODE_SVC 0x13 362#define I_BIT 0x80 363 364/* 365 * use bad_save_user_regs for abort/prefetch/undef/swi ... 366 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 367 */ 368 369 .macro bad_save_user_regs 370 @ carve out a frame on current user stack 371 sub sp, sp, #S_FRAME_SIZE 372 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 373 ldr r2, IRQ_STACK_START_IN 374 @ get values for "aborted" pc and cpsr (into parm regs) 375 ldmia r2, {r2 - r3} 376 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 377 add r5, sp, #S_SP 378 mov r1, lr 379 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 380 mov r0, sp @ save current stack into r0 (param register) 381 .endm 382 383 .macro irq_save_user_regs 384 sub sp, sp, #S_FRAME_SIZE 385 stmia sp, {r0 - r12} @ Calling r0-r12 386 @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 387 add r8, sp, #S_PC 388 stmdb r8, {sp, lr}^ @ Calling SP, LR 389 str lr, [r8, #0] @ Save calling PC 390 mrs r6, spsr 391 str r6, [r8, #4] @ Save CPSR 392 str r0, [r8, #8] @ Save OLD_R0 393 mov r0, sp 394 .endm 395 396 .macro irq_restore_user_regs 397 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 398 mov r0, r0 399 ldr lr, [sp, #S_PC] @ Get PC 400 add sp, sp, #S_FRAME_SIZE 401 subs pc, lr, #4 @ return & move spsr_svc into cpsr 402 .endm 403 404 .macro get_bad_stack 405 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 406 407 str lr, [r13] @ save caller lr in position 0 of saved stack 408 mrs lr, spsr @ get the spsr 409 str lr, [r13, #4] @ save spsr in position 1 of saved stack 410 mov r13, #MODE_SVC @ prepare SVC-Mode 411 @ msr spsr_c, r13 412 msr spsr, r13 @ switch modes, make sure moves will execute 413 mov lr, pc @ capture return pc 414 movs pc, lr @ jump to next instruction & switch modes. 415 .endm 416 417 .macro get_irq_stack @ setup IRQ stack 418 ldr sp, IRQ_STACK_START 419 .endm 420 421 .macro get_fiq_stack @ setup FIQ stack 422 ldr sp, FIQ_STACK_START 423 .endm 424#endif /* CONFIG_SPL_BUILD */ 425 426/* 427 * exception handlers 428 */ 429#ifdef CONFIG_SPL_BUILD 430 .align 5 431do_hang: 432 ldr sp, _TEXT_BASE /* switch to abort stack */ 4331: 434 bl 1b /* hang and never return */ 435#else /* !CONFIG_SPL_BUILD */ 436 .align 5 437undefined_instruction: 438 get_bad_stack 439 bad_save_user_regs 440 bl do_undefined_instruction 441 442 .align 5 443software_interrupt: 444 get_bad_stack 445 bad_save_user_regs 446 bl do_software_interrupt 447 448 .align 5 449prefetch_abort: 450 get_bad_stack 451 bad_save_user_regs 452 bl do_prefetch_abort 453 454 .align 5 455data_abort: 456 get_bad_stack 457 bad_save_user_regs 458 bl do_data_abort 459 460 .align 5 461not_used: 462 get_bad_stack 463 bad_save_user_regs 464 bl do_not_used 465 466#ifdef CONFIG_USE_IRQ 467 468 .align 5 469irq: 470 get_irq_stack 471 irq_save_user_regs 472 bl do_irq 473 irq_restore_user_regs 474 475 .align 5 476fiq: 477 get_fiq_stack 478 /* someone ought to write a more effiction fiq_save_user_regs */ 479 irq_save_user_regs 480 bl do_fiq 481 irq_restore_user_regs 482 483#else 484 485 .align 5 486irq: 487 get_bad_stack 488 bad_save_user_regs 489 bl do_irq 490 491 .align 5 492fiq: 493 get_bad_stack 494 bad_save_user_regs 495 bl do_fiq 496 497#endif 498#endif /* CONFIG_SPL_BUILD */ 499