1/* 2 * armboot - Startup Code for ARM926EJS CPU-core 3 * 4 * Copyright (c) 2003 Texas Instruments 5 * 6 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ 7 * 8 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 9 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 10 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 12 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 13 * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net> 14 * 15 * See file CREDITS for list of people who contributed to this 16 * project. 17 * 18 * This program is free software; you can redistribute it and/or 19 * modify it under the terms of the GNU General Public License as 20 * published by the Free Software Foundation; either version 2 of 21 * the License, or (at your option) any later version. 22 * 23 * This program is distributed in the hope that it will be useful, 24 * but WITHOUT ANY WARRANTY; without even the implied warranty of 25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 * GNU General Public License for more details. 27 * 28 * You should have received a copy of the GNU General Public License 29 * along with this program; if not, write to the Free Software 30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 31 * MA 02111-1307 USA 32 */ 33 34#include <asm-offsets.h> 35#include <config.h> 36#include <common.h> 37#include <version.h> 38 39/* 40 ************************************************************************* 41 * 42 * Jump vector table as in table 3.1 in [1] 43 * 44 ************************************************************************* 45 */ 46 47 48#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG 49.globl _start 50_start: 51.globl _NOR_BOOT_CFG 52_NOR_BOOT_CFG: 53 .word CONFIG_SYS_DV_NOR_BOOT_CFG 54 b reset 55#else 56.globl _start 57_start: 58 b reset 59#endif 60#ifdef CONFIG_SPL_BUILD 61/* No exception handlers in preloader */ 62 ldr pc, _hang 63 ldr pc, _hang 64 ldr pc, _hang 65 ldr pc, _hang 66 ldr pc, _hang 67 ldr pc, _hang 68 ldr pc, _hang 69 70_hang: 71 .word do_hang 72/* pad to 64 byte boundary */ 73 .word 0x12345678 74 .word 0x12345678 75 .word 0x12345678 76 .word 0x12345678 77 .word 0x12345678 78 .word 0x12345678 79 .word 0x12345678 80#else 81 ldr pc, _undefined_instruction 82 ldr pc, _software_interrupt 83 ldr pc, _prefetch_abort 84 ldr pc, _data_abort 85 ldr pc, _not_used 86 ldr pc, _irq 87 ldr pc, _fiq 88 89_undefined_instruction: 90 .word undefined_instruction 91_software_interrupt: 92 .word software_interrupt 93_prefetch_abort: 94 .word prefetch_abort 95_data_abort: 96 .word data_abort 97_not_used: 98 .word not_used 99_irq: 100 .word irq 101_fiq: 102 .word fiq 103 104#endif /* CONFIG_SPL_BUILD */ 105 .balignl 16,0xdeadbeef 106 107 108/* 109 ************************************************************************* 110 * 111 * Startup Code (reset vector) 112 * 113 * do important init only if we don't start from memory! 114 * setup Memory and board specific bits prior to relocation. 115 * relocate armboot to ram 116 * setup stack 117 * 118 ************************************************************************* 119 */ 120 121.globl _TEXT_BASE 122_TEXT_BASE: 123#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */ 124 .word CONFIG_SYS_TEXT_BASE 125#else 126#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) 127 .word CONFIG_SPL_TEXT_BASE 128#else 129 .word CONFIG_SYS_TEXT_BASE 130#endif 131#endif 132 133/* 134 * These are defined in the board-specific linker script. 135 * Subtracting _start from them lets the linker put their 136 * relative position in the executable instead of leaving 137 * them null. 138 */ 139.globl _bss_start_ofs 140_bss_start_ofs: 141 .word __bss_start - _start 142 143.globl _bss_end_ofs 144_bss_end_ofs: 145 .word __bss_end - _start 146 147.globl _end_ofs 148_end_ofs: 149 .word _end - _start 150 151#ifdef CONFIG_NAND_U_BOOT 152.globl _end 153_end: 154 .word __bss_end 155#endif 156 157#ifdef CONFIG_USE_IRQ 158/* IRQ stack memory (calculated at run-time) */ 159.globl IRQ_STACK_START 160IRQ_STACK_START: 161 .word 0x0badc0de 162 163/* IRQ stack memory (calculated at run-time) */ 164.globl FIQ_STACK_START 165FIQ_STACK_START: 166 .word 0x0badc0de 167#endif 168 169/* IRQ stack memory (calculated at run-time) + 8 bytes */ 170.globl IRQ_STACK_START_IN 171IRQ_STACK_START_IN: 172 .word 0x0badc0de 173 174/* 175 * the actual reset code 176 */ 177 178reset: 179 /* 180 * set the cpu to SVC32 mode 181 */ 182 mrs r0,cpsr 183 bic r0,r0,#0x1f 184 orr r0,r0,#0xd3 185 msr cpsr,r0 186 187 /* 188 * we do sys-critical inits only at reboot, 189 * not when booting from ram! 190 */ 191#ifndef CONFIG_SKIP_LOWLEVEL_INIT 192 bl cpu_init_crit 193#endif 194 195 bl _main 196 197/*------------------------------------------------------------------------------*/ 198 199#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_NAND_SPL) 200/* 201 * void relocate_code (addr_sp, gd, addr_moni) 202 * 203 * This function relocates the monitor code. 204 */ 205 .globl relocate_code 206relocate_code: 207 mov r4, r0 /* save addr_sp */ 208 mov r5, r1 /* save addr of gd */ 209 mov r6, r2 /* save addr of destination */ 210 211 adr r0, _start 212 subs r9, r6, r0 /* r9 <- relocation offset */ 213 beq relocate_done /* skip relocation */ 214 mov r1, r6 /* r1 <- scratch for copy loop */ 215 ldr r3, _bss_start_ofs 216 add r2, r0, r3 /* r2 <- source end address */ 217 218copy_loop: 219 ldmia r0!, {r10-r11} /* copy from source address [r0] */ 220 stmia r1!, {r10-r11} /* copy to target address [r1] */ 221 cmp r0, r2 /* until source end address [r2] */ 222 blo copy_loop 223 224#ifndef CONFIG_SPL_BUILD 225 /* 226 * fix .rel.dyn relocations 227 */ 228 ldr r0, _TEXT_BASE /* r0 <- Text base */ 229 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 230 add r10, r10, r0 /* r10 <- sym table in FLASH */ 231 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 232 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 233 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 234 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 235fixloop: 236 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 237 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 238 ldr r1, [r2, #4] 239 and r7, r1, #0xff 240 cmp r7, #23 /* relative fixup? */ 241 beq fixrel 242 cmp r7, #2 /* absolute fixup? */ 243 beq fixabs 244 /* ignore unknown type of fixup */ 245 b fixnext 246fixabs: 247 /* absolute fix: set location to (offset) symbol value */ 248 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 249 add r1, r10, r1 /* r1 <- address of symbol in table */ 250 ldr r1, [r1, #4] /* r1 <- symbol value */ 251 add r1, r1, r9 /* r1 <- relocated sym addr */ 252 b fixnext 253fixrel: 254 /* relative fix: increase location by offset */ 255 ldr r1, [r0] 256 add r1, r1, r9 257fixnext: 258 str r1, [r0] 259 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 260 cmp r2, r3 261 blo fixloop 262#endif 263 264relocate_done: 265 266 bx lr 267 268_rel_dyn_start_ofs: 269 .word __rel_dyn_start - _start 270_rel_dyn_end_ofs: 271 .word __rel_dyn_end - _start 272_dynsym_start_ofs: 273 .word __dynsym_start - _start 274 275#endif 276 277 .globl c_runtime_cpu_setup 278c_runtime_cpu_setup: 279 280 bx lr 281 282/* 283 ************************************************************************* 284 * 285 * CPU_init_critical registers 286 * 287 * setup important registers 288 * setup memory timing 289 * 290 ************************************************************************* 291 */ 292#ifndef CONFIG_SKIP_LOWLEVEL_INIT 293cpu_init_crit: 294 /* 295 * flush D cache before disabling it 296 */ 297 mov r0, #0 298flush_dcache: 299 mrc p15, 0, r15, c7, c10, 3 300 bne flush_dcache 301 302 mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */ 303 mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */ 304 305 /* 306 * disable MMU and D cache 307 * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined 308 */ 309 mrc p15, 0, r0, c1, c0, 0 310 bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */ 311 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ 312#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH 313 orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */ 314#else 315 bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ 316#endif 317 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ 318#ifndef CONFIG_SYS_ICACHE_OFF 319 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ 320#endif 321 mcr p15, 0, r0, c1, c0, 0 322 323 /* 324 * Go setup Memory and board specific bits prior to relocation. 325 */ 326 mov ip, lr /* perserve link reg across call */ 327 bl lowlevel_init /* go setup pll,mux,memory */ 328 mov lr, ip /* restore link */ 329 mov pc, lr /* back to my caller */ 330#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 331 332#ifndef CONFIG_SPL_BUILD 333/* 334 ************************************************************************* 335 * 336 * Interrupt handling 337 * 338 ************************************************************************* 339 */ 340 341@ 342@ IRQ stack frame. 343@ 344#define S_FRAME_SIZE 72 345 346#define S_OLD_R0 68 347#define S_PSR 64 348#define S_PC 60 349#define S_LR 56 350#define S_SP 52 351 352#define S_IP 48 353#define S_FP 44 354#define S_R10 40 355#define S_R9 36 356#define S_R8 32 357#define S_R7 28 358#define S_R6 24 359#define S_R5 20 360#define S_R4 16 361#define S_R3 12 362#define S_R2 8 363#define S_R1 4 364#define S_R0 0 365 366#define MODE_SVC 0x13 367#define I_BIT 0x80 368 369/* 370 * use bad_save_user_regs for abort/prefetch/undef/swi ... 371 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 372 */ 373 374 .macro bad_save_user_regs 375 @ carve out a frame on current user stack 376 sub sp, sp, #S_FRAME_SIZE 377 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 378 ldr r2, IRQ_STACK_START_IN 379 @ get values for "aborted" pc and cpsr (into parm regs) 380 ldmia r2, {r2 - r3} 381 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 382 add r5, sp, #S_SP 383 mov r1, lr 384 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 385 mov r0, sp @ save current stack into r0 (param register) 386 .endm 387 388 .macro irq_save_user_regs 389 sub sp, sp, #S_FRAME_SIZE 390 stmia sp, {r0 - r12} @ Calling r0-r12 391 @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 392 add r8, sp, #S_PC 393 stmdb r8, {sp, lr}^ @ Calling SP, LR 394 str lr, [r8, #0] @ Save calling PC 395 mrs r6, spsr 396 str r6, [r8, #4] @ Save CPSR 397 str r0, [r8, #8] @ Save OLD_R0 398 mov r0, sp 399 .endm 400 401 .macro irq_restore_user_regs 402 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 403 mov r0, r0 404 ldr lr, [sp, #S_PC] @ Get PC 405 add sp, sp, #S_FRAME_SIZE 406 subs pc, lr, #4 @ return & move spsr_svc into cpsr 407 .endm 408 409 .macro get_bad_stack 410 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 411 412 str lr, [r13] @ save caller lr in position 0 of saved stack 413 mrs lr, spsr @ get the spsr 414 str lr, [r13, #4] @ save spsr in position 1 of saved stack 415 mov r13, #MODE_SVC @ prepare SVC-Mode 416 @ msr spsr_c, r13 417 msr spsr, r13 @ switch modes, make sure moves will execute 418 mov lr, pc @ capture return pc 419 movs pc, lr @ jump to next instruction & switch modes. 420 .endm 421 422 .macro get_irq_stack @ setup IRQ stack 423 ldr sp, IRQ_STACK_START 424 .endm 425 426 .macro get_fiq_stack @ setup FIQ stack 427 ldr sp, FIQ_STACK_START 428 .endm 429#endif /* CONFIG_SPL_BUILD */ 430 431/* 432 * exception handlers 433 */ 434#ifdef CONFIG_SPL_BUILD 435 .align 5 436do_hang: 437 ldr sp, _TEXT_BASE /* switch to abort stack */ 4381: 439 bl 1b /* hang and never return */ 440#else /* !CONFIG_SPL_BUILD */ 441 .align 5 442undefined_instruction: 443 get_bad_stack 444 bad_save_user_regs 445 bl do_undefined_instruction 446 447 .align 5 448software_interrupt: 449 get_bad_stack 450 bad_save_user_regs 451 bl do_software_interrupt 452 453 .align 5 454prefetch_abort: 455 get_bad_stack 456 bad_save_user_regs 457 bl do_prefetch_abort 458 459 .align 5 460data_abort: 461 get_bad_stack 462 bad_save_user_regs 463 bl do_data_abort 464 465 .align 5 466not_used: 467 get_bad_stack 468 bad_save_user_regs 469 bl do_not_used 470 471#ifdef CONFIG_USE_IRQ 472 473 .align 5 474irq: 475 get_irq_stack 476 irq_save_user_regs 477 bl do_irq 478 irq_restore_user_regs 479 480 .align 5 481fiq: 482 get_fiq_stack 483 /* someone ought to write a more effiction fiq_save_user_regs */ 484 irq_save_user_regs 485 bl do_fiq 486 irq_restore_user_regs 487 488#else 489 490 .align 5 491irq: 492 get_bad_stack 493 bad_save_user_regs 494 bl do_irq 495 496 .align 5 497fiq: 498 get_bad_stack 499 bad_save_user_regs 500 bl do_fiq 501 502#endif 503#endif /* CONFIG_SPL_BUILD */ 504