1/* 2 * armboot - Startup Code for ARM926EJS CPU-core 3 * 4 * Copyright (c) 2003 Texas Instruments 5 * 6 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ 7 * 8 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 9 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 10 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 12 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 13 * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net> 14 * 15 * See file CREDITS for list of people who contributed to this 16 * project. 17 * 18 * This program is free software; you can redistribute it and/or 19 * modify it under the terms of the GNU General Public License as 20 * published by the Free Software Foundation; either version 2 of 21 * the License, or (at your option) any later version. 22 * 23 * This program is distributed in the hope that it will be useful, 24 * but WITHOUT ANY WARRANTY; without even the implied warranty of 25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 * GNU General Public License for more details. 27 * 28 * You should have received a copy of the GNU General Public License 29 * along with this program; if not, write to the Free Software 30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 31 * MA 02111-1307 USA 32 */ 33 34#include <asm-offsets.h> 35#include <config.h> 36#include <common.h> 37#include <version.h> 38 39#if defined(CONFIG_OMAP1610) 40#include <./configs/omap1510.h> 41#elif defined(CONFIG_OMAP730) 42#include <./configs/omap730.h> 43#endif 44 45/* 46 ************************************************************************* 47 * 48 * Jump vector table as in table 3.1 in [1] 49 * 50 ************************************************************************* 51 */ 52 53 54#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG 55.globl _start 56_start: 57.globl _NOR_BOOT_CFG 58_NOR_BOOT_CFG: 59 .word CONFIG_SYS_DV_NOR_BOOT_CFG 60 b reset 61#else 62.globl _start 63_start: 64 b reset 65#endif 66#ifdef CONFIG_SPL_BUILD 67/* No exception handlers in preloader */ 68 ldr pc, _hang 69 ldr pc, _hang 70 ldr pc, _hang 71 ldr pc, _hang 72 ldr pc, _hang 73 ldr pc, _hang 74 ldr pc, _hang 75 76_hang: 77 .word do_hang 78/* pad to 64 byte boundary */ 79 .word 0x12345678 80 .word 0x12345678 81 .word 0x12345678 82 .word 0x12345678 83 .word 0x12345678 84 .word 0x12345678 85 .word 0x12345678 86#else 87 ldr pc, _undefined_instruction 88 ldr pc, _software_interrupt 89 ldr pc, _prefetch_abort 90 ldr pc, _data_abort 91 ldr pc, _not_used 92 ldr pc, _irq 93 ldr pc, _fiq 94 95_undefined_instruction: 96 .word undefined_instruction 97_software_interrupt: 98 .word software_interrupt 99_prefetch_abort: 100 .word prefetch_abort 101_data_abort: 102 .word data_abort 103_not_used: 104 .word not_used 105_irq: 106 .word irq 107_fiq: 108 .word fiq 109 110#endif /* CONFIG_SPL_BUILD */ 111 .balignl 16,0xdeadbeef 112 113 114/* 115 ************************************************************************* 116 * 117 * Startup Code (reset vector) 118 * 119 * do important init only if we don't start from memory! 120 * setup Memory and board specific bits prior to relocation. 121 * relocate armboot to ram 122 * setup stack 123 * 124 ************************************************************************* 125 */ 126 127.globl _TEXT_BASE 128_TEXT_BASE: 129 .word CONFIG_SYS_TEXT_BASE 130 131/* 132 * These are defined in the board-specific linker script. 133 * Subtracting _start from them lets the linker put their 134 * relative position in the executable instead of leaving 135 * them null. 136 */ 137.globl _bss_start_ofs 138_bss_start_ofs: 139 .word __bss_start - _start 140 141.globl _bss_end_ofs 142_bss_end_ofs: 143 .word __bss_end__ - _start 144 145.globl _end_ofs 146_end_ofs: 147 .word _end - _start 148 149#ifdef CONFIG_NAND_U_BOOT 150.globl _end 151_end: 152 .word __bss_end__ 153#endif 154 155#ifdef CONFIG_USE_IRQ 156/* IRQ stack memory (calculated at run-time) */ 157.globl IRQ_STACK_START 158IRQ_STACK_START: 159 .word 0x0badc0de 160 161/* IRQ stack memory (calculated at run-time) */ 162.globl FIQ_STACK_START 163FIQ_STACK_START: 164 .word 0x0badc0de 165#endif 166 167/* IRQ stack memory (calculated at run-time) + 8 bytes */ 168.globl IRQ_STACK_START_IN 169IRQ_STACK_START_IN: 170 .word 0x0badc0de 171 172/* 173 * the actual reset code 174 */ 175 176reset: 177 /* 178 * set the cpu to SVC32 mode 179 */ 180 mrs r0,cpsr 181 bic r0,r0,#0x1f 182 orr r0,r0,#0xd3 183 msr cpsr,r0 184 185 /* 186 * we do sys-critical inits only at reboot, 187 * not when booting from ram! 188 */ 189#ifndef CONFIG_SKIP_LOWLEVEL_INIT 190 bl cpu_init_crit 191#endif 192 193/* Set stackpointer in internal RAM to call board_init_f */ 194call_board_init_f: 195 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 196 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 197 ldr r0,=0x00000000 198 bl board_init_f 199 200/*------------------------------------------------------------------------------*/ 201 202/* 203 * void relocate_code (addr_sp, gd, addr_moni) 204 * 205 * This "function" does not return, instead it continues in RAM 206 * after relocating the monitor code. 207 * 208 */ 209 .globl relocate_code 210relocate_code: 211 mov r4, r0 /* save addr_sp */ 212 mov r5, r1 /* save addr of gd */ 213 mov r6, r2 /* save addr of destination */ 214 215 /* Set up the stack */ 216stack_setup: 217 mov sp, r4 218 219 adr r0, _start 220 cmp r0, r6 221 beq clear_bss /* skip relocation */ 222 mov r1, r6 /* r1 <- scratch for copy loop */ 223 ldr r3, _bss_start_ofs 224 add r2, r0, r3 /* r2 <- source end address */ 225 226copy_loop: 227 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 228 stmia r1!, {r9-r10} /* copy to target address [r1] */ 229 cmp r0, r2 /* until source end address [r2] */ 230 blo copy_loop 231 232#ifndef CONFIG_SPL_BUILD 233 /* 234 * fix .rel.dyn relocations 235 */ 236 ldr r0, _TEXT_BASE /* r0 <- Text base */ 237 sub r9, r6, r0 /* r9 <- relocation offset */ 238 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 239 add r10, r10, r0 /* r10 <- sym table in FLASH */ 240 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 241 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 242 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 243 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 244fixloop: 245 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 246 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 247 ldr r1, [r2, #4] 248 and r7, r1, #0xff 249 cmp r7, #23 /* relative fixup? */ 250 beq fixrel 251 cmp r7, #2 /* absolute fixup? */ 252 beq fixabs 253 /* ignore unknown type of fixup */ 254 b fixnext 255fixabs: 256 /* absolute fix: set location to (offset) symbol value */ 257 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 258 add r1, r10, r1 /* r1 <- address of symbol in table */ 259 ldr r1, [r1, #4] /* r1 <- symbol value */ 260 add r1, r1, r9 /* r1 <- relocated sym addr */ 261 b fixnext 262fixrel: 263 /* relative fix: increase location by offset */ 264 ldr r1, [r0] 265 add r1, r1, r9 266fixnext: 267 str r1, [r0] 268 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 269 cmp r2, r3 270 blo fixloop 271#endif 272 273clear_bss: 274#ifndef CONFIG_SPL_BUILD 275 ldr r0, _bss_start_ofs 276 ldr r1, _bss_end_ofs 277 mov r4, r6 /* reloc addr */ 278 add r0, r0, r4 279 add r1, r1, r4 280 mov r2, #0x00000000 /* clear */ 281 282clbss_l:str r2, [r0] /* clear loop... */ 283 add r0, r0, #4 284 cmp r0, r1 285 bne clbss_l 286 287 bl coloured_LED_init 288 bl red_led_on 289#endif 290 291/* 292 * We are done. Do not return, instead branch to second part of board 293 * initialization, now running from RAM. 294 */ 295#ifdef CONFIG_NAND_SPL 296 ldr r0, _nand_boot_ofs 297 mov pc, r0 298 299_nand_boot_ofs: 300 .word nand_boot 301#else 302 ldr r0, _board_init_r_ofs 303 ldr r1, _TEXT_BASE 304 add lr, r0, r1 305 add lr, lr, r9 306 /* setup parameters for board_init_r */ 307 mov r0, r5 /* gd_t */ 308 mov r1, r6 /* dest_addr */ 309 /* jump to it ... */ 310 mov pc, lr 311 312_board_init_r_ofs: 313 .word board_init_r - _start 314#endif 315 316_rel_dyn_start_ofs: 317 .word __rel_dyn_start - _start 318_rel_dyn_end_ofs: 319 .word __rel_dyn_end - _start 320_dynsym_start_ofs: 321 .word __dynsym_start - _start 322 323/* 324 ************************************************************************* 325 * 326 * CPU_init_critical registers 327 * 328 * setup important registers 329 * setup memory timing 330 * 331 ************************************************************************* 332 */ 333#ifndef CONFIG_SKIP_LOWLEVEL_INIT 334cpu_init_crit: 335 /* 336 * flush v4 I/D caches 337 */ 338 mov r0, #0 339 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 340 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 341 342 /* 343 * disable MMU stuff and caches 344 */ 345 mrc p15, 0, r0, c1, c0, 0 346 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ 347 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ 348 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ 349 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ 350 mcr p15, 0, r0, c1, c0, 0 351 352 /* 353 * Go setup Memory and board specific bits prior to relocation. 354 */ 355 mov ip, lr /* perserve link reg across call */ 356 bl lowlevel_init /* go setup pll,mux,memory */ 357 mov lr, ip /* restore link */ 358 mov pc, lr /* back to my caller */ 359#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 360 361#ifndef CONFIG_SPL_BUILD 362/* 363 ************************************************************************* 364 * 365 * Interrupt handling 366 * 367 ************************************************************************* 368 */ 369 370@ 371@ IRQ stack frame. 372@ 373#define S_FRAME_SIZE 72 374 375#define S_OLD_R0 68 376#define S_PSR 64 377#define S_PC 60 378#define S_LR 56 379#define S_SP 52 380 381#define S_IP 48 382#define S_FP 44 383#define S_R10 40 384#define S_R9 36 385#define S_R8 32 386#define S_R7 28 387#define S_R6 24 388#define S_R5 20 389#define S_R4 16 390#define S_R3 12 391#define S_R2 8 392#define S_R1 4 393#define S_R0 0 394 395#define MODE_SVC 0x13 396#define I_BIT 0x80 397 398/* 399 * use bad_save_user_regs for abort/prefetch/undef/swi ... 400 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 401 */ 402 403 .macro bad_save_user_regs 404 @ carve out a frame on current user stack 405 sub sp, sp, #S_FRAME_SIZE 406 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 407 ldr r2, IRQ_STACK_START_IN 408 @ get values for "aborted" pc and cpsr (into parm regs) 409 ldmia r2, {r2 - r3} 410 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 411 add r5, sp, #S_SP 412 mov r1, lr 413 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 414 mov r0, sp @ save current stack into r0 (param register) 415 .endm 416 417 .macro irq_save_user_regs 418 sub sp, sp, #S_FRAME_SIZE 419 stmia sp, {r0 - r12} @ Calling r0-r12 420 @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 421 add r8, sp, #S_PC 422 stmdb r8, {sp, lr}^ @ Calling SP, LR 423 str lr, [r8, #0] @ Save calling PC 424 mrs r6, spsr 425 str r6, [r8, #4] @ Save CPSR 426 str r0, [r8, #8] @ Save OLD_R0 427 mov r0, sp 428 .endm 429 430 .macro irq_restore_user_regs 431 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 432 mov r0, r0 433 ldr lr, [sp, #S_PC] @ Get PC 434 add sp, sp, #S_FRAME_SIZE 435 subs pc, lr, #4 @ return & move spsr_svc into cpsr 436 .endm 437 438 .macro get_bad_stack 439 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 440 441 str lr, [r13] @ save caller lr in position 0 of saved stack 442 mrs lr, spsr @ get the spsr 443 str lr, [r13, #4] @ save spsr in position 1 of saved stack 444 mov r13, #MODE_SVC @ prepare SVC-Mode 445 @ msr spsr_c, r13 446 msr spsr, r13 @ switch modes, make sure moves will execute 447 mov lr, pc @ capture return pc 448 movs pc, lr @ jump to next instruction & switch modes. 449 .endm 450 451 .macro get_irq_stack @ setup IRQ stack 452 ldr sp, IRQ_STACK_START 453 .endm 454 455 .macro get_fiq_stack @ setup FIQ stack 456 ldr sp, FIQ_STACK_START 457 .endm 458#endif /* CONFIG_SPL_BUILD */ 459 460/* 461 * exception handlers 462 */ 463#ifdef CONFIG_SPL_BUILD 464 .align 5 465do_hang: 466 ldr sp, _TEXT_BASE /* switch to abort stack */ 4671: 468 bl 1b /* hang and never return */ 469#else /* !CONFIG_SPL_BUILD */ 470 .align 5 471undefined_instruction: 472 get_bad_stack 473 bad_save_user_regs 474 bl do_undefined_instruction 475 476 .align 5 477software_interrupt: 478 get_bad_stack 479 bad_save_user_regs 480 bl do_software_interrupt 481 482 .align 5 483prefetch_abort: 484 get_bad_stack 485 bad_save_user_regs 486 bl do_prefetch_abort 487 488 .align 5 489data_abort: 490 get_bad_stack 491 bad_save_user_regs 492 bl do_data_abort 493 494 .align 5 495not_used: 496 get_bad_stack 497 bad_save_user_regs 498 bl do_not_used 499 500#ifdef CONFIG_USE_IRQ 501 502 .align 5 503irq: 504 get_irq_stack 505 irq_save_user_regs 506 bl do_irq 507 irq_restore_user_regs 508 509 .align 5 510fiq: 511 get_fiq_stack 512 /* someone ought to write a more effiction fiq_save_user_regs */ 513 irq_save_user_regs 514 bl do_fiq 515 irq_restore_user_regs 516 517#else 518 519 .align 5 520irq: 521 get_bad_stack 522 bad_save_user_regs 523 bl do_irq 524 525 .align 5 526fiq: 527 get_bad_stack 528 bad_save_user_regs 529 bl do_fiq 530 531#endif 532#endif /* CONFIG_SPL_BUILD */ 533