xref: /rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/spear/cpu.c (revision 225bfd3906453c13a0a88b03d8e62a2f267b3689)
1962d026bSVipin KUMAR /*
2962d026bSVipin KUMAR  * (C) Copyright 2010
3962d026bSVipin KUMAR  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
4962d026bSVipin KUMAR  *
51a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
6962d026bSVipin KUMAR  */
7962d026bSVipin KUMAR 
8962d026bSVipin KUMAR #include <common.h>
9962d026bSVipin KUMAR #include <asm/io.h>
10962d026bSVipin KUMAR #include <asm/arch/hardware.h>
11962d026bSVipin KUMAR #include <asm/arch/spr_misc.h>
12962d026bSVipin KUMAR 
arch_cpu_init(void)13962d026bSVipin KUMAR int arch_cpu_init(void)
14962d026bSVipin KUMAR {
15962d026bSVipin KUMAR 	struct misc_regs *const misc_p =
16962d026bSVipin KUMAR 	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
177c885a0eSShiraz Hashim 	u32 periph1_clken, periph_clk_cfg;
18962d026bSVipin KUMAR 
19962d026bSVipin KUMAR 	periph1_clken = readl(&misc_p->periph1_clken);
20962d026bSVipin KUMAR 
21962d026bSVipin KUMAR #if defined(CONFIG_SPEAR3XX)
22962d026bSVipin KUMAR 	periph1_clken |= MISC_GPT2ENB;
23962d026bSVipin KUMAR #elif defined(CONFIG_SPEAR600)
24962d026bSVipin KUMAR 	periph1_clken |= MISC_GPT3ENB;
25962d026bSVipin KUMAR #endif
26962d026bSVipin KUMAR 
27962d026bSVipin KUMAR #if defined(CONFIG_PL011_SERIAL)
28962d026bSVipin KUMAR 	periph1_clken |= MISC_UART0ENB;
297c885a0eSShiraz Hashim 
307c885a0eSShiraz Hashim 	periph_clk_cfg = readl(&misc_p->periph_clk_cfg);
317c885a0eSShiraz Hashim 	periph_clk_cfg &= ~CONFIG_SPEAR_UARTCLKMSK;
327c885a0eSShiraz Hashim 	periph_clk_cfg |= CONFIG_SPEAR_UART48M;
337c885a0eSShiraz Hashim 	writel(periph_clk_cfg, &misc_p->periph_clk_cfg);
34962d026bSVipin KUMAR #endif
35ef48f6ddSSimon Glass #if defined(CONFIG_ETH_DESIGNWARE)
36962d026bSVipin KUMAR 	periph1_clken |= MISC_ETHENB;
37962d026bSVipin KUMAR #endif
38962d026bSVipin KUMAR #if defined(CONFIG_DW_UDC)
39962d026bSVipin KUMAR 	periph1_clken |= MISC_USBDENB;
40962d026bSVipin KUMAR #endif
41678398b1SStefan Roese #if defined(CONFIG_SYS_I2C_DW)
42962d026bSVipin KUMAR 	periph1_clken |= MISC_I2CENB;
43962d026bSVipin KUMAR #endif
44962d026bSVipin KUMAR #if defined(CONFIG_ST_SMI)
45962d026bSVipin KUMAR 	periph1_clken |= MISC_SMIENB;
46962d026bSVipin KUMAR #endif
47962d026bSVipin KUMAR #if defined(CONFIG_NAND_FSMC)
48962d026bSVipin KUMAR 	periph1_clken |= MISC_FSMCENB;
49962d026bSVipin KUMAR #endif
50e8d05698SStefan Roese #if defined(CONFIG_USB_EHCI_SPEAR)
51e8d05698SStefan Roese 	periph1_clken |= PERIPH_USBH1 | PERIPH_USBH2;
52e8d05698SStefan Roese #endif
53962d026bSVipin KUMAR 
54962d026bSVipin KUMAR 	writel(periph1_clken, &misc_p->periph1_clken);
55e8d05698SStefan Roese 
56962d026bSVipin KUMAR 	return 0;
57962d026bSVipin KUMAR }
58962d026bSVipin KUMAR 
enable_caches(void)59f49cc22fSStefan Roese void enable_caches(void)
60f49cc22fSStefan Roese {
61f49cc22fSStefan Roese #ifndef CONFIG_SYS_ICACHE_OFF
62f49cc22fSStefan Roese 	icache_enable();
63f49cc22fSStefan Roese #endif
64f49cc22fSStefan Roese #ifndef CONFIG_SYS_DCACHE_OFF
65f49cc22fSStefan Roese 	dcache_enable();
66f49cc22fSStefan Roese #endif
67f49cc22fSStefan Roese }
68f49cc22fSStefan Roese 
69962d026bSVipin KUMAR #ifdef CONFIG_DISPLAY_CPUINFO
print_cpuinfo(void)70962d026bSVipin KUMAR int print_cpuinfo(void)
71962d026bSVipin KUMAR {
72962d026bSVipin KUMAR #ifdef CONFIG_SPEAR300
73962d026bSVipin KUMAR 	printf("CPU:   SPEAr300\n");
74962d026bSVipin KUMAR #elif defined(CONFIG_SPEAR310)
75962d026bSVipin KUMAR 	printf("CPU:   SPEAr310\n");
76962d026bSVipin KUMAR #elif defined(CONFIG_SPEAR320)
77962d026bSVipin KUMAR 	printf("CPU:   SPEAr320\n");
78962d026bSVipin KUMAR #elif defined(CONFIG_SPEAR600)
79962d026bSVipin KUMAR 	printf("CPU:   SPEAr600\n");
80962d026bSVipin KUMAR #else
81962d026bSVipin KUMAR #error CPU not supported in spear platform
82962d026bSVipin KUMAR #endif
83962d026bSVipin KUMAR 	return 0;
84962d026bSVipin KUMAR }
85962d026bSVipin KUMAR #endif
86da53ba02SStefan Roese 
87*225bfd39SThomas Petazzoni #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH) && defined(CONFIG_NAND_FSMC)
do_switch_ecc(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])88da53ba02SStefan Roese static int do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc,
89da53ba02SStefan Roese 			 char *const argv[])
90da53ba02SStefan Roese {
91da53ba02SStefan Roese 	if (argc != 2)
92da53ba02SStefan Roese 		goto usage;
93da53ba02SStefan Roese 
94da53ba02SStefan Roese 	if (strncmp(argv[1], "hw", 2) == 0) {
95da53ba02SStefan Roese 		/* 1-bit HW ECC */
96da53ba02SStefan Roese 		printf("Switching to 1-bit HW ECC\n");
97da53ba02SStefan Roese 		fsmc_nand_switch_ecc(1);
98da53ba02SStefan Roese 	} else if (strncmp(argv[1], "bch4", 2) == 0) {
99da53ba02SStefan Roese 		/* 4-bit SW ECC BCH4 */
100da53ba02SStefan Roese 		printf("Switching to 4-bit SW ECC (BCH4)\n");
101da53ba02SStefan Roese 		fsmc_nand_switch_ecc(4);
102da53ba02SStefan Roese 	} else {
103da53ba02SStefan Roese 		goto usage;
104da53ba02SStefan Roese 	}
105da53ba02SStefan Roese 
106da53ba02SStefan Roese 	return 0;
107da53ba02SStefan Roese 
108da53ba02SStefan Roese usage:
109da53ba02SStefan Roese 	printf("Usage: nandecc %s\n", cmdtp->usage);
110da53ba02SStefan Roese 	return 1;
111da53ba02SStefan Roese }
112da53ba02SStefan Roese 
113da53ba02SStefan Roese U_BOOT_CMD(
114da53ba02SStefan Roese 	nandecc, 2, 0,	do_switch_ecc,
115da53ba02SStefan Roese 	"switch NAND ECC calculation algorithm",
116da53ba02SStefan Roese 	"hw|bch4 - Switch between NAND hardware 1-bit HW and"
117da53ba02SStefan Roese 	" 4-bit SW BCH\n"
118da53ba02SStefan Roese );
119da53ba02SStefan Roese #endif
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