1 /* 2 * (C) Copyright 2009 DENX Software Engineering 3 * Author: John Rigby <jrigby@gmail.com> 4 * 5 * Based on mx27/generic.c: 6 * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org> 7 * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <div64.h> 27 #include <netdev.h> 28 #include <asm/io.h> 29 #include <asm/arch/imx-regs.h> 30 #include <asm/arch/imx25-pinmux.h> 31 #include <asm/arch/clock.h> 32 #ifdef CONFIG_MXC_MMC 33 #include <asm/arch/mxcmmc.h> 34 #endif 35 36 #ifdef CONFIG_FSL_ESDHC 37 DECLARE_GLOBAL_DATA_PTR; 38 #endif 39 40 /* 41 * get the system pll clock in Hz 42 * 43 * mfi + mfn / (mfd +1) 44 * f = 2 * f_ref * -------------------- 45 * pd + 1 46 */ 47 static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref) 48 { 49 unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT) 50 & CCM_PLL_MFI_MASK; 51 int mfn = (pll >> CCM_PLL_MFN_SHIFT) 52 & CCM_PLL_MFN_MASK; 53 unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT) 54 & CCM_PLL_MFD_MASK; 55 unsigned int pd = (pll >> CCM_PLL_PD_SHIFT) 56 & CCM_PLL_PD_MASK; 57 58 mfi = mfi <= 5 ? 5 : mfi; 59 mfn = mfn >= 512 ? mfn - 1024 : mfn; 60 mfd += 1; 61 pd += 1; 62 63 return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn), 64 mfd * pd); 65 } 66 67 static ulong imx_get_mpllclk(void) 68 { 69 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; 70 ulong fref = MXC_HCLK; 71 72 return imx_decode_pll(readl(&ccm->mpctl), fref); 73 } 74 75 ulong imx_get_armclk(void) 76 { 77 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; 78 ulong cctl = readl(&ccm->cctl); 79 ulong fref = imx_get_mpllclk(); 80 ulong div; 81 82 if (cctl & CCM_CCTL_ARM_SRC) 83 fref = lldiv((u64) fref * 3, 4); 84 85 div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT) 86 & CCM_CCTL_ARM_DIV_MASK) + 1; 87 88 return fref / div; 89 } 90 91 ulong imx_get_ahbclk(void) 92 { 93 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; 94 ulong cctl = readl(&ccm->cctl); 95 ulong fref = imx_get_armclk(); 96 ulong div; 97 98 div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT) 99 & CCM_CCTL_AHB_DIV_MASK) + 1; 100 101 return fref / div; 102 } 103 104 ulong imx_get_perclk(int clk) 105 { 106 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; 107 ulong fref = imx_get_ahbclk(); 108 ulong div; 109 110 div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]); 111 div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1; 112 113 return fref / div; 114 } 115 116 unsigned int mxc_get_clock(enum mxc_clock clk) 117 { 118 if (clk >= MXC_CLK_NUM) 119 return -1; 120 switch (clk) { 121 case MXC_ARM_CLK: 122 return imx_get_armclk(); 123 case MXC_FEC_CLK: 124 return imx_get_ahbclk(); 125 default: 126 return imx_get_perclk(clk); 127 } 128 } 129 130 u32 get_cpu_rev(void) 131 { 132 u32 srev; 133 u32 system_rev = 0x25000; 134 135 /* read SREV register from IIM module */ 136 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; 137 srev = readl(&iim->iim_srev); 138 139 switch (srev) { 140 case 0x00: 141 system_rev |= CHIP_REV_1_0; 142 break; 143 case 0x01: 144 system_rev |= CHIP_REV_1_1; 145 break; 146 case 0x02: 147 system_rev |= CHIP_REV_1_2; 148 break; 149 default: 150 system_rev |= 0x8000; 151 break; 152 } 153 154 return system_rev; 155 } 156 157 #if defined(CONFIG_DISPLAY_CPUINFO) 158 static char *get_reset_cause(void) 159 { 160 /* read RCSR register from CCM module */ 161 struct ccm_regs *ccm = 162 (struct ccm_regs *)IMX_CCM_BASE; 163 164 u32 cause = readl(&ccm->rcsr) & 0x0f; 165 166 if (cause == 0) 167 return "POR"; 168 else if (cause == 1) 169 return "RST"; 170 else if ((cause & 2) == 2) 171 return "WDOG"; 172 else if ((cause & 4) == 4) 173 return "SW RESET"; 174 else if ((cause & 8) == 8) 175 return "JTAG"; 176 else 177 return "unknown reset"; 178 179 } 180 181 int print_cpuinfo(void) 182 { 183 char buf[32]; 184 u32 cpurev = get_cpu_rev(); 185 186 printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n", 187 (cpurev & 0xF0) >> 4, (cpurev & 0x0F), 188 ((cpurev & 0x8000) ? " unknown" : ""), 189 strmhz(buf, imx_get_armclk())); 190 printf("Reset cause: %s\n\n", get_reset_cause()); 191 return 0; 192 } 193 #endif 194 195 void enable_caches(void) 196 { 197 #ifndef CONFIG_SYS_DCACHE_OFF 198 /* Enable D-cache. I-cache is already enabled in start.S */ 199 dcache_enable(); 200 #endif 201 } 202 203 int cpu_eth_init(bd_t *bis) 204 { 205 #if defined(CONFIG_FEC_MXC) 206 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; 207 ulong val; 208 209 val = readl(&ccm->cgr0); 210 val |= (1 << 23); 211 writel(val, &ccm->cgr0); 212 return fecmxc_initialize(bis); 213 #else 214 return 0; 215 #endif 216 } 217 218 int get_clocks(void) 219 { 220 #ifdef CONFIG_FSL_ESDHC 221 gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 222 #endif 223 return 0; 224 } 225 226 /* 227 * Initializes on-chip MMC controllers. 228 * to override, implement board_mmc_init() 229 */ 230 int cpu_mmc_init(bd_t *bis) 231 { 232 #ifdef CONFIG_MXC_MMC 233 return mxc_mmc_init(bis); 234 #else 235 return 0; 236 #endif 237 } 238 239 #ifdef CONFIG_MXC_UART 240 void mx25_uart1_init_pins(void) 241 { 242 struct iomuxc_mux_ctl *muxctl; 243 struct iomuxc_pad_ctl *padctl; 244 u32 inpadctl; 245 u32 outpadctl; 246 u32 muxmode0; 247 248 muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; 249 padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; 250 muxmode0 = MX25_PIN_MUX_MODE(0); 251 /* 252 * set up input pins with hysteresis and 100K pull-ups 253 */ 254 inpadctl = MX25_PIN_PAD_CTL_HYS 255 | MX25_PIN_PAD_CTL_PKE 256 | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PU; 257 258 /* 259 * set up output pins with 100K pull-downs 260 * FIXME: need to revisit this 261 * PUE is ignored if PKE is not set 262 * so the right value here is likely 263 * 0x0 for no pull up/down 264 * or 265 * 0xc0 for 100k pull down 266 */ 267 outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD; 268 269 /* UART1 */ 270 /* rxd */ 271 writel(muxmode0, &muxctl->pad_uart1_rxd); 272 writel(inpadctl, &padctl->pad_uart1_rxd); 273 274 /* txd */ 275 writel(muxmode0, &muxctl->pad_uart1_txd); 276 writel(outpadctl, &padctl->pad_uart1_txd); 277 278 /* rts */ 279 writel(muxmode0, &muxctl->pad_uart1_rts); 280 writel(outpadctl, &padctl->pad_uart1_rts); 281 282 /* cts */ 283 writel(muxmode0, &muxctl->pad_uart1_cts); 284 writel(inpadctl, &padctl->pad_uart1_cts); 285 } 286 #endif /* CONFIG_MXC_UART */ 287 288 #ifdef CONFIG_FEC_MXC 289 void mx25_fec_init_pins(void) 290 { 291 struct iomuxc_mux_ctl *muxctl; 292 struct iomuxc_pad_ctl *padctl; 293 u32 inpadctl_100kpd; 294 u32 inpadctl_22kpu; 295 u32 outpadctl; 296 u32 muxmode0; 297 298 muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; 299 padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; 300 muxmode0 = MX25_PIN_MUX_MODE(0); 301 inpadctl_100kpd = MX25_PIN_PAD_CTL_HYS 302 | MX25_PIN_PAD_CTL_PKE 303 | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD; 304 inpadctl_22kpu = MX25_PIN_PAD_CTL_HYS 305 | MX25_PIN_PAD_CTL_PKE 306 | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_22K_PU; 307 /* 308 * set up output pins with 100K pull-downs 309 * FIXME: need to revisit this 310 * PUE is ignored if PKE is not set 311 * so the right value here is likely 312 * 0x0 for no pull 313 * or 314 * 0xc0 for 100k pull down 315 */ 316 outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD; 317 318 /* FEC_TX_CLK */ 319 writel(muxmode0, &muxctl->pad_fec_tx_clk); 320 writel(inpadctl_100kpd, &padctl->pad_fec_tx_clk); 321 322 /* FEC_RX_DV */ 323 writel(muxmode0, &muxctl->pad_fec_rx_dv); 324 writel(inpadctl_100kpd, &padctl->pad_fec_rx_dv); 325 326 /* FEC_RDATA0 */ 327 writel(muxmode0, &muxctl->pad_fec_rdata0); 328 writel(inpadctl_100kpd, &padctl->pad_fec_rdata0); 329 330 /* FEC_TDATA0 */ 331 writel(muxmode0, &muxctl->pad_fec_tdata0); 332 writel(outpadctl, &padctl->pad_fec_tdata0); 333 334 /* FEC_TX_EN */ 335 writel(muxmode0, &muxctl->pad_fec_tx_en); 336 writel(outpadctl, &padctl->pad_fec_tx_en); 337 338 /* FEC_MDC */ 339 writel(muxmode0, &muxctl->pad_fec_mdc); 340 writel(outpadctl, &padctl->pad_fec_mdc); 341 342 /* FEC_MDIO */ 343 writel(muxmode0, &muxctl->pad_fec_mdio); 344 writel(inpadctl_22kpu, &padctl->pad_fec_mdio); 345 346 /* FEC_RDATA1 */ 347 writel(muxmode0, &muxctl->pad_fec_rdata1); 348 writel(inpadctl_100kpd, &padctl->pad_fec_rdata1); 349 350 /* FEC_TDATA1 */ 351 writel(muxmode0, &muxctl->pad_fec_tdata1); 352 writel(outpadctl, &padctl->pad_fec_tdata1); 353 354 } 355 356 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) 357 { 358 int i; 359 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; 360 struct fuse_bank *bank = &iim->bank[0]; 361 struct fuse_bank0_regs *fuse = 362 (struct fuse_bank0_regs *)bank->fuse_regs; 363 364 for (i = 0; i < 6; i++) 365 mac[i] = readl(&fuse->mac_addr[i]) & 0xff; 366 } 367 #endif /* CONFIG_FEC_MXC */ 368