1 /* 2 * (C) Copyright 2009 DENX Software Engineering 3 * Author: John Rigby <jrigby@gmail.com> 4 * 5 * Based on mx27/generic.c: 6 * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org> 7 * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <div64.h> 27 #include <netdev.h> 28 #include <asm/io.h> 29 #include <asm/arch/imx-regs.h> 30 #include <asm/arch/imx25-pinmux.h> 31 #include <asm/arch/clock.h> 32 #ifdef CONFIG_MXC_MMC 33 #include <asm/arch/mxcmmc.h> 34 #endif 35 36 #ifdef CONFIG_FSL_ESDHC 37 DECLARE_GLOBAL_DATA_PTR; 38 #endif 39 40 /* 41 * get the system pll clock in Hz 42 * 43 * mfi + mfn / (mfd +1) 44 * f = 2 * f_ref * -------------------- 45 * pd + 1 46 */ 47 static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref) 48 { 49 unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT) 50 & CCM_PLL_MFI_MASK; 51 int mfn = (pll >> CCM_PLL_MFN_SHIFT) 52 & CCM_PLL_MFN_MASK; 53 unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT) 54 & CCM_PLL_MFD_MASK; 55 unsigned int pd = (pll >> CCM_PLL_PD_SHIFT) 56 & CCM_PLL_PD_MASK; 57 58 mfi = mfi <= 5 ? 5 : mfi; 59 mfn = mfn >= 512 ? mfn - 1024 : mfn; 60 mfd += 1; 61 pd += 1; 62 63 return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn), 64 mfd * pd); 65 } 66 67 static ulong imx_get_mpllclk(void) 68 { 69 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; 70 ulong fref = MXC_HCLK; 71 72 return imx_decode_pll(readl(&ccm->mpctl), fref); 73 } 74 75 ulong imx_get_armclk(void) 76 { 77 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; 78 ulong cctl = readl(&ccm->cctl); 79 ulong fref = imx_get_mpllclk(); 80 ulong div; 81 82 if (cctl & CCM_CCTL_ARM_SRC) 83 fref = lldiv((u64) fref * 3, 4); 84 85 div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT) 86 & CCM_CCTL_ARM_DIV_MASK) + 1; 87 88 return fref / div; 89 } 90 91 ulong imx_get_ahbclk(void) 92 { 93 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; 94 ulong cctl = readl(&ccm->cctl); 95 ulong fref = imx_get_armclk(); 96 ulong div; 97 98 div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT) 99 & CCM_CCTL_AHB_DIV_MASK) + 1; 100 101 return fref / div; 102 } 103 104 static ulong imx_get_ipgclk(void) 105 { 106 return imx_get_ahbclk() / 2; 107 } 108 109 ulong imx_get_perclk(int clk) 110 { 111 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; 112 ulong fref = imx_get_ahbclk(); 113 ulong div; 114 115 div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]); 116 div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1; 117 118 return fref / div; 119 } 120 121 unsigned int mxc_get_clock(enum mxc_clock clk) 122 { 123 if (clk >= MXC_CLK_NUM) 124 return -1; 125 switch (clk) { 126 case MXC_ARM_CLK: 127 return imx_get_armclk(); 128 case MXC_AHB_CLK: 129 return imx_get_ahbclk(); 130 case MXC_IPG_CLK: 131 case MXC_CSPI_CLK: 132 return imx_get_ipgclk(); 133 case MXC_FEC_CLK: 134 return imx_get_ahbclk(); 135 default: 136 return imx_get_perclk(clk); 137 } 138 } 139 140 u32 get_cpu_rev(void) 141 { 142 u32 srev; 143 u32 system_rev = 0x25000; 144 145 /* read SREV register from IIM module */ 146 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; 147 srev = readl(&iim->iim_srev); 148 149 switch (srev) { 150 case 0x00: 151 system_rev |= CHIP_REV_1_0; 152 break; 153 case 0x01: 154 system_rev |= CHIP_REV_1_1; 155 break; 156 case 0x02: 157 system_rev |= CHIP_REV_1_2; 158 break; 159 default: 160 system_rev |= 0x8000; 161 break; 162 } 163 164 return system_rev; 165 } 166 167 #if defined(CONFIG_DISPLAY_CPUINFO) 168 static char *get_reset_cause(void) 169 { 170 /* read RCSR register from CCM module */ 171 struct ccm_regs *ccm = 172 (struct ccm_regs *)IMX_CCM_BASE; 173 174 u32 cause = readl(&ccm->rcsr) & 0x0f; 175 176 if (cause == 0) 177 return "POR"; 178 else if (cause == 1) 179 return "RST"; 180 else if ((cause & 2) == 2) 181 return "WDOG"; 182 else if ((cause & 4) == 4) 183 return "SW RESET"; 184 else if ((cause & 8) == 8) 185 return "JTAG"; 186 else 187 return "unknown reset"; 188 189 } 190 191 int print_cpuinfo(void) 192 { 193 char buf[32]; 194 u32 cpurev = get_cpu_rev(); 195 196 printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n", 197 (cpurev & 0xF0) >> 4, (cpurev & 0x0F), 198 ((cpurev & 0x8000) ? " unknown" : ""), 199 strmhz(buf, imx_get_armclk())); 200 printf("Reset cause: %s\n\n", get_reset_cause()); 201 return 0; 202 } 203 #endif 204 205 void enable_caches(void) 206 { 207 #ifndef CONFIG_SYS_DCACHE_OFF 208 /* Enable D-cache. I-cache is already enabled in start.S */ 209 dcache_enable(); 210 #endif 211 } 212 213 int cpu_eth_init(bd_t *bis) 214 { 215 #if defined(CONFIG_FEC_MXC) 216 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; 217 ulong val; 218 219 val = readl(&ccm->cgr0); 220 val |= (1 << 23); 221 writel(val, &ccm->cgr0); 222 return fecmxc_initialize(bis); 223 #else 224 return 0; 225 #endif 226 } 227 228 int get_clocks(void) 229 { 230 #ifdef CONFIG_FSL_ESDHC 231 gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 232 #endif 233 return 0; 234 } 235 236 /* 237 * Initializes on-chip MMC controllers. 238 * to override, implement board_mmc_init() 239 */ 240 int cpu_mmc_init(bd_t *bis) 241 { 242 #ifdef CONFIG_MXC_MMC 243 return mxc_mmc_init(bis); 244 #else 245 return 0; 246 #endif 247 } 248 249 #ifdef CONFIG_MXC_UART 250 void mx25_uart1_init_pins(void) 251 { 252 struct iomuxc_mux_ctl *muxctl; 253 struct iomuxc_pad_ctl *padctl; 254 u32 inpadctl; 255 u32 outpadctl; 256 u32 muxmode0; 257 258 muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; 259 padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; 260 muxmode0 = MX25_PIN_MUX_MODE(0); 261 /* 262 * set up input pins with hysteresis and 100K pull-ups 263 */ 264 inpadctl = MX25_PIN_PAD_CTL_HYS 265 | MX25_PIN_PAD_CTL_PKE 266 | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PU; 267 268 /* 269 * set up output pins with 100K pull-downs 270 * FIXME: need to revisit this 271 * PUE is ignored if PKE is not set 272 * so the right value here is likely 273 * 0x0 for no pull up/down 274 * or 275 * 0xc0 for 100k pull down 276 */ 277 outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD; 278 279 /* UART1 */ 280 /* rxd */ 281 writel(muxmode0, &muxctl->pad_uart1_rxd); 282 writel(inpadctl, &padctl->pad_uart1_rxd); 283 284 /* txd */ 285 writel(muxmode0, &muxctl->pad_uart1_txd); 286 writel(outpadctl, &padctl->pad_uart1_txd); 287 288 /* rts */ 289 writel(muxmode0, &muxctl->pad_uart1_rts); 290 writel(outpadctl, &padctl->pad_uart1_rts); 291 292 /* cts */ 293 writel(muxmode0, &muxctl->pad_uart1_cts); 294 writel(inpadctl, &padctl->pad_uart1_cts); 295 } 296 #endif /* CONFIG_MXC_UART */ 297 298 #ifdef CONFIG_FEC_MXC 299 void mx25_fec_init_pins(void) 300 { 301 struct iomuxc_mux_ctl *muxctl; 302 struct iomuxc_pad_ctl *padctl; 303 u32 inpadctl_100kpd; 304 u32 inpadctl_22kpu; 305 u32 outpadctl; 306 u32 muxmode0; 307 308 muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; 309 padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; 310 muxmode0 = MX25_PIN_MUX_MODE(0); 311 inpadctl_100kpd = MX25_PIN_PAD_CTL_HYS 312 | MX25_PIN_PAD_CTL_PKE 313 | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD; 314 inpadctl_22kpu = MX25_PIN_PAD_CTL_HYS 315 | MX25_PIN_PAD_CTL_PKE 316 | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_22K_PU; 317 /* 318 * set up output pins with 100K pull-downs 319 * FIXME: need to revisit this 320 * PUE is ignored if PKE is not set 321 * so the right value here is likely 322 * 0x0 for no pull 323 * or 324 * 0xc0 for 100k pull down 325 */ 326 outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD; 327 328 /* FEC_TX_CLK */ 329 writel(muxmode0, &muxctl->pad_fec_tx_clk); 330 writel(inpadctl_100kpd, &padctl->pad_fec_tx_clk); 331 332 /* FEC_RX_DV */ 333 writel(muxmode0, &muxctl->pad_fec_rx_dv); 334 writel(inpadctl_100kpd, &padctl->pad_fec_rx_dv); 335 336 /* FEC_RDATA0 */ 337 writel(muxmode0, &muxctl->pad_fec_rdata0); 338 writel(inpadctl_100kpd, &padctl->pad_fec_rdata0); 339 340 /* FEC_TDATA0 */ 341 writel(muxmode0, &muxctl->pad_fec_tdata0); 342 writel(outpadctl, &padctl->pad_fec_tdata0); 343 344 /* FEC_TX_EN */ 345 writel(muxmode0, &muxctl->pad_fec_tx_en); 346 writel(outpadctl, &padctl->pad_fec_tx_en); 347 348 /* FEC_MDC */ 349 writel(muxmode0, &muxctl->pad_fec_mdc); 350 writel(outpadctl, &padctl->pad_fec_mdc); 351 352 /* FEC_MDIO */ 353 writel(muxmode0, &muxctl->pad_fec_mdio); 354 writel(inpadctl_22kpu, &padctl->pad_fec_mdio); 355 356 /* FEC_RDATA1 */ 357 writel(muxmode0, &muxctl->pad_fec_rdata1); 358 writel(inpadctl_100kpd, &padctl->pad_fec_rdata1); 359 360 /* FEC_TDATA1 */ 361 writel(muxmode0, &muxctl->pad_fec_tdata1); 362 writel(outpadctl, &padctl->pad_fec_tdata1); 363 364 } 365 366 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) 367 { 368 int i; 369 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; 370 struct fuse_bank *bank = &iim->bank[0]; 371 struct fuse_bank0_regs *fuse = 372 (struct fuse_bank0_regs *)bank->fuse_regs; 373 374 for (i = 0; i < 6; i++) 375 mac[i] = readl(&fuse->mac_addr[i]) & 0xff; 376 } 377 #endif /* CONFIG_FEC_MXC */ 378