1 /* 2 * (C) Copyright 2009 DENX Software Engineering 3 * Author: John Rigby <jrigby@gmail.com> 4 * 5 * Based on mx27/generic.c: 6 * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org> 7 * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <div64.h> 27 #include <netdev.h> 28 #include <asm/io.h> 29 #include <asm/arch/imx-regs.h> 30 #include <asm/arch/imx25-pinmux.h> 31 #ifdef CONFIG_MXC_MMC 32 #include <asm/arch/mxcmmc.h> 33 #endif 34 35 /* 36 * get the system pll clock in Hz 37 * 38 * mfi + mfn / (mfd +1) 39 * f = 2 * f_ref * -------------------- 40 * pd + 1 41 */ 42 static unsigned int imx_decode_pll (unsigned int pll, unsigned int f_ref) 43 { 44 unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT) 45 & CCM_PLL_MFI_MASK; 46 unsigned int mfn = (pll >> CCM_PLL_MFN_SHIFT) 47 & CCM_PLL_MFN_MASK; 48 unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT) 49 & CCM_PLL_MFD_MASK; 50 unsigned int pd = (pll >> CCM_PLL_PD_SHIFT) 51 & CCM_PLL_PD_MASK; 52 53 mfi = mfi <= 5 ? 5 : mfi; 54 55 return lldiv (2 * (u64) f_ref * (mfi * (mfd + 1) + mfn), 56 (mfd + 1) * (pd + 1)); 57 } 58 59 static ulong imx_get_mpllclk (void) 60 { 61 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; 62 ulong fref = 24000000; 63 64 return imx_decode_pll (readl (&ccm->mpctl), fref); 65 } 66 67 ulong imx_get_armclk (void) 68 { 69 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; 70 ulong cctl = readl (&ccm->cctl); 71 ulong fref = imx_get_mpllclk (); 72 ulong div; 73 74 if (cctl & CCM_CCTL_ARM_SRC) 75 fref = lldiv ((fref * 3), 4); 76 77 div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT) 78 & CCM_CCTL_ARM_DIV_MASK) + 1; 79 80 return lldiv (fref, div); 81 } 82 83 ulong imx_get_ahbclk (void) 84 { 85 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; 86 ulong cctl = readl (&ccm->cctl); 87 ulong fref = imx_get_armclk (); 88 ulong div; 89 90 div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT) 91 & CCM_CCTL_AHB_DIV_MASK) + 1; 92 93 return lldiv (fref, div); 94 } 95 96 ulong imx_get_perclk (int clk) 97 { 98 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; 99 ulong fref = imx_get_ahbclk (); 100 ulong div; 101 102 div = readl (&ccm->pcdr[CCM_PERCLK_REG (clk)]); 103 div = ((div >> CCM_PERCLK_SHIFT (clk)) & CCM_PERCLK_MASK) + 1; 104 105 return lldiv (fref, div); 106 } 107 108 109 u32 get_cpu_rev(void) 110 { 111 u32 srev; 112 u32 system_rev = 0x25000; 113 114 /* read SREV register from IIM module */ 115 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; 116 srev = readl(&iim->iim_srev); 117 118 switch (srev) { 119 case 0x00: 120 system_rev |= CHIP_REV_1_0; 121 break; 122 case 0x01: 123 system_rev |= CHIP_REV_1_1; 124 break; 125 default: 126 system_rev |= 0x8000; 127 break; 128 } 129 130 return system_rev; 131 } 132 133 #if defined(CONFIG_DISPLAY_CPUINFO) 134 int print_cpuinfo (void) 135 { 136 char buf[32]; 137 u32 cpurev = get_cpu_rev(); 138 139 printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n\n", 140 (cpurev & 0xF0) >> 4, (cpurev & 0x0F), 141 ((cpurev & 0x8000) ? " unknown" : ""), 142 strmhz (buf, imx_get_armclk ())); 143 return 0; 144 } 145 #endif 146 147 int cpu_eth_init (bd_t * bis) 148 { 149 #if defined(CONFIG_FEC_MXC) 150 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; 151 ulong val; 152 153 val = readl (&ccm->cgr0); 154 val |= (1 << 23); 155 writel (val, &ccm->cgr0); 156 return fecmxc_initialize (bis); 157 #else 158 return 0; 159 #endif 160 } 161 162 /* 163 * Initializes on-chip MMC controllers. 164 * to override, implement board_mmc_init() 165 */ 166 int cpu_mmc_init (bd_t * bis) 167 { 168 #ifdef CONFIG_MXC_MMC 169 return mxc_mmc_init (bis); 170 #else 171 return 0; 172 #endif 173 } 174 175 #ifdef CONFIG_MXC_UART 176 void mx25_uart1_init_pins(void) 177 { 178 struct iomuxc_mux_ctl *muxctl; 179 struct iomuxc_pad_ctl *padctl; 180 u32 inpadctl; 181 u32 outpadctl; 182 u32 muxmode0; 183 184 muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; 185 padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; 186 muxmode0 = MX25_PIN_MUX_MODE (0); 187 /* 188 * set up input pins with hysteresis and 100K pull-ups 189 */ 190 inpadctl = MX25_PIN_PAD_CTL_HYS 191 | MX25_PIN_PAD_CTL_PKE 192 | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PU; 193 194 /* 195 * set up output pins with 100K pull-downs 196 * FIXME: need to revisit this 197 * PUE is ignored if PKE is not set 198 * so the right value here is likely 199 * 0x0 for no pull up/down 200 * or 201 * 0xc0 for 100k pull down 202 */ 203 outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD; 204 205 /* UART1 */ 206 /* rxd */ 207 writel (muxmode0, &muxctl->pad_uart1_rxd); 208 writel (inpadctl, &padctl->pad_uart1_rxd); 209 210 /* txd */ 211 writel (muxmode0, &muxctl->pad_uart1_txd); 212 writel (outpadctl, &padctl->pad_uart1_txd); 213 214 /* rts */ 215 writel (muxmode0, &muxctl->pad_uart1_rts); 216 writel (outpadctl, &padctl->pad_uart1_rts); 217 218 /* cts */ 219 writel (muxmode0, &muxctl->pad_uart1_cts); 220 writel (inpadctl, &padctl->pad_uart1_cts); 221 } 222 #endif /* CONFIG_MXC_UART */ 223 224 #ifdef CONFIG_FEC_MXC 225 void mx25_fec_init_pins (void) 226 { 227 struct iomuxc_mux_ctl *muxctl; 228 struct iomuxc_pad_ctl *padctl; 229 u32 inpadctl_100kpd; 230 u32 inpadctl_22kpu; 231 u32 outpadctl; 232 u32 muxmode0; 233 234 muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; 235 padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; 236 muxmode0 = MX25_PIN_MUX_MODE (0); 237 inpadctl_100kpd = MX25_PIN_PAD_CTL_HYS 238 | MX25_PIN_PAD_CTL_PKE 239 | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD; 240 inpadctl_22kpu = MX25_PIN_PAD_CTL_HYS 241 | MX25_PIN_PAD_CTL_PKE 242 | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_22K_PU; 243 /* 244 * set up output pins with 100K pull-downs 245 * FIXME: need to revisit this 246 * PUE is ignored if PKE is not set 247 * so the right value here is likely 248 * 0x0 for no pull 249 * or 250 * 0xc0 for 100k pull down 251 */ 252 outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD; 253 254 /* FEC_TX_CLK */ 255 writel (muxmode0, &muxctl->pad_fec_tx_clk); 256 writel (inpadctl_100kpd, &padctl->pad_fec_tx_clk); 257 258 /* FEC_RX_DV */ 259 writel (muxmode0, &muxctl->pad_fec_rx_dv); 260 writel (inpadctl_100kpd, &padctl->pad_fec_rx_dv); 261 262 /* FEC_RDATA0 */ 263 writel (muxmode0, &muxctl->pad_fec_rdata0); 264 writel (inpadctl_100kpd, &padctl->pad_fec_rdata0); 265 266 /* FEC_TDATA0 */ 267 writel (muxmode0, &muxctl->pad_fec_tdata0); 268 writel (outpadctl, &padctl->pad_fec_tdata0); 269 270 /* FEC_TX_EN */ 271 writel (muxmode0, &muxctl->pad_fec_tx_en); 272 writel (outpadctl, &padctl->pad_fec_tx_en); 273 274 /* FEC_MDC */ 275 writel (muxmode0, &muxctl->pad_fec_mdc); 276 writel (outpadctl, &padctl->pad_fec_mdc); 277 278 /* FEC_MDIO */ 279 writel (muxmode0, &muxctl->pad_fec_mdio); 280 writel (inpadctl_22kpu, &padctl->pad_fec_mdio); 281 282 /* FEC_RDATA1 */ 283 writel (muxmode0, &muxctl->pad_fec_rdata1); 284 writel (inpadctl_100kpd, &padctl->pad_fec_rdata1); 285 286 /* FEC_TDATA1 */ 287 writel (muxmode0, &muxctl->pad_fec_tdata1); 288 writel (outpadctl, &padctl->pad_fec_tdata1); 289 290 } 291 292 void imx_get_mac_from_fuse(unsigned char *mac) 293 { 294 int i; 295 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; 296 struct fuse_bank *bank = &iim->bank[0]; 297 struct fuse_bank0_regs *fuse = 298 (struct fuse_bank0_regs *)bank->fuse_regs; 299 300 for (i = 0; i < 6; i++) 301 mac[i] = readl(&fuse->mac_addr[i]) & 0xff; 302 } 303 #endif /* CONFIG_FEC_MXC */ 304