1/* 2 * armboot - Startup Code for ARM920 CPU-core 3 * 4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 6 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27#include <asm-offsets.h> 28#include <common.h> 29#include <config.h> 30 31/* 32 ************************************************************************* 33 * 34 * Jump vector table as in table 3.1 in [1] 35 * 36 ************************************************************************* 37 */ 38 39 40.globl _start 41_start: b start_code 42 ldr pc, _undefined_instruction 43 ldr pc, _software_interrupt 44 ldr pc, _prefetch_abort 45 ldr pc, _data_abort 46 ldr pc, _not_used 47 ldr pc, _irq 48 ldr pc, _fiq 49 50_undefined_instruction: .word undefined_instruction 51_software_interrupt: .word software_interrupt 52_prefetch_abort: .word prefetch_abort 53_data_abort: .word data_abort 54_not_used: .word not_used 55_irq: .word irq 56_fiq: .word fiq 57 58 .balignl 16,0xdeadbeef 59 60 61/* 62 ************************************************************************* 63 * 64 * Startup Code (called from the ARM reset exception vector) 65 * 66 * do important init only if we don't start from memory! 67 * relocate armboot to ram 68 * setup stack 69 * jump to second stage 70 * 71 ************************************************************************* 72 */ 73 74.globl _TEXT_BASE 75_TEXT_BASE: 76#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) 77 .word CONFIG_SPL_TEXT_BASE 78#else 79 .word CONFIG_SYS_TEXT_BASE 80#endif 81 82/* 83 * These are defined in the board-specific linker script. 84 * Subtracting _start from them lets the linker put their 85 * relative position in the executable instead of leaving 86 * them null. 87 */ 88.globl _bss_start_ofs 89_bss_start_ofs: 90 .word __bss_start - _start 91 92.globl _bss_end_ofs 93_bss_end_ofs: 94 .word __bss_end - _start 95 96.globl _end_ofs 97_end_ofs: 98 .word _end - _start 99 100#ifdef CONFIG_USE_IRQ 101/* IRQ stack memory (calculated at run-time) */ 102.globl IRQ_STACK_START 103IRQ_STACK_START: 104 .word 0x0badc0de 105 106/* IRQ stack memory (calculated at run-time) */ 107.globl FIQ_STACK_START 108FIQ_STACK_START: 109 .word 0x0badc0de 110#endif 111 112/* IRQ stack memory (calculated at run-time) + 8 bytes */ 113.globl IRQ_STACK_START_IN 114IRQ_STACK_START_IN: 115 .word 0x0badc0de 116 117/* 118 * the actual start code 119 */ 120 121start_code: 122 /* 123 * set the cpu to SVC32 mode 124 */ 125 mrs r0, cpsr 126 bic r0, r0, #0x1f 127 orr r0, r0, #0xd3 128 msr cpsr, r0 129 130#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) 131 /* 132 * relocate exception table 133 */ 134 ldr r0, =_start 135 ldr r1, =0x0 136 mov r2, #16 137copyex: 138 subs r2, r2, #1 139 ldr r3, [r0], #4 140 str r3, [r1], #4 141 bne copyex 142#endif 143 144#ifdef CONFIG_S3C24X0 145 /* turn off the watchdog */ 146 147# if defined(CONFIG_S3C2400) 148# define pWTCON 0x15300000 149# define INTMSK 0x14400008 /* Interrupt-Controller base addresses */ 150# define CLKDIVN 0x14800014 /* clock divisor register */ 151#else 152# define pWTCON 0x53000000 153# define INTMSK 0x4A000008 /* Interrupt-Controller base addresses */ 154# define INTSUBMSK 0x4A00001C 155# define CLKDIVN 0x4C000014 /* clock divisor register */ 156# endif 157 158 ldr r0, =pWTCON 159 mov r1, #0x0 160 str r1, [r0] 161 162 /* 163 * mask all IRQs by setting all bits in the INTMR - default 164 */ 165 mov r1, #0xffffffff 166 ldr r0, =INTMSK 167 str r1, [r0] 168# if defined(CONFIG_S3C2410) 169 ldr r1, =0x3ff 170 ldr r0, =INTSUBMSK 171 str r1, [r0] 172# endif 173 174 /* FCLK:HCLK:PCLK = 1:2:4 */ 175 /* default FCLK is 120 MHz ! */ 176 ldr r0, =CLKDIVN 177 mov r1, #3 178 str r1, [r0] 179#endif /* CONFIG_S3C24X0 */ 180 181 /* 182 * we do sys-critical inits only at reboot, 183 * not when booting from ram! 184 */ 185#ifndef CONFIG_SKIP_LOWLEVEL_INIT 186 bl cpu_init_crit 187#endif 188 189 bl _main 190 191/*------------------------------------------------------------------------------*/ 192 193/* 194 * void relocate_code (addr_sp, gd, addr_moni) 195 * 196 * This "function" does not return, instead it continues in RAM 197 * after relocating the monitor code. 198 * 199 */ 200 .globl relocate_code 201relocate_code: 202 mov r4, r0 /* save addr_sp */ 203 mov r5, r1 /* save addr of gd */ 204 mov r6, r2 /* save addr of destination */ 205 206 adr r0, _start 207 cmp r0, r6 208 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ 209 beq relocate_done /* skip relocation */ 210 mov r1, r6 /* r1 <- scratch for copy_loop */ 211 ldr r3, _bss_start_ofs 212 add r2, r0, r3 /* r2 <- source end address */ 213 214copy_loop: 215 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 216 stmia r1!, {r9-r10} /* copy to target address [r1] */ 217 cmp r0, r2 /* until source end address [r2] */ 218 blo copy_loop 219 220#ifndef CONFIG_SPL_BUILD 221 /* 222 * fix .rel.dyn relocations 223 */ 224 ldr r0, _TEXT_BASE /* r0 <- Text base */ 225 sub r9, r6, r0 /* r9 <- relocation offset */ 226 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 227 add r10, r10, r0 /* r10 <- sym table in FLASH */ 228 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 229 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 230 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 231 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 232fixloop: 233 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 234 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 235 ldr r1, [r2, #4] 236 and r7, r1, #0xff 237 cmp r7, #23 /* relative fixup? */ 238 beq fixrel 239 cmp r7, #2 /* absolute fixup? */ 240 beq fixabs 241 /* ignore unknown type of fixup */ 242 b fixnext 243fixabs: 244 /* absolute fix: set location to (offset) symbol value */ 245 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 246 add r1, r10, r1 /* r1 <- address of symbol in table */ 247 ldr r1, [r1, #4] /* r1 <- symbol value */ 248 add r1, r1, r9 /* r1 <- relocated sym addr */ 249 b fixnext 250fixrel: 251 /* relative fix: increase location by offset */ 252 ldr r1, [r0] 253 add r1, r1, r9 254fixnext: 255 str r1, [r0] 256 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 257 cmp r2, r3 258 blo fixloop 259#endif 260 261relocate_done: 262 263 mov pc, lr 264 265_rel_dyn_start_ofs: 266 .word __rel_dyn_start - _start 267_rel_dyn_end_ofs: 268 .word __rel_dyn_end - _start 269_dynsym_start_ofs: 270 .word __dynsym_start - _start 271 272 .globl c_runtime_cpu_setup 273c_runtime_cpu_setup: 274 275 mov pc, lr 276 277/* 278 ************************************************************************* 279 * 280 * CPU_init_critical registers 281 * 282 * setup important registers 283 * setup memory timing 284 * 285 ************************************************************************* 286 */ 287 288 289#ifndef CONFIG_SKIP_LOWLEVEL_INIT 290cpu_init_crit: 291 /* 292 * flush v4 I/D caches 293 */ 294 mov r0, #0 295 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 296 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 297 298 /* 299 * disable MMU stuff and caches 300 */ 301 mrc p15, 0, r0, c1, c0, 0 302 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 303 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 304 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 305 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 306 mcr p15, 0, r0, c1, c0, 0 307 308 /* 309 * before relocating, we have to setup RAM timing 310 * because memory timing is board-dependend, you will 311 * find a lowlevel_init.S in your board directory. 312 */ 313 mov ip, lr 314 315 bl lowlevel_init 316 317 mov lr, ip 318 mov pc, lr 319#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 320 321/* 322 ************************************************************************* 323 * 324 * Interrupt handling 325 * 326 ************************************************************************* 327 */ 328 329@ 330@ IRQ stack frame. 331@ 332#define S_FRAME_SIZE 72 333 334#define S_OLD_R0 68 335#define S_PSR 64 336#define S_PC 60 337#define S_LR 56 338#define S_SP 52 339 340#define S_IP 48 341#define S_FP 44 342#define S_R10 40 343#define S_R9 36 344#define S_R8 32 345#define S_R7 28 346#define S_R6 24 347#define S_R5 20 348#define S_R4 16 349#define S_R3 12 350#define S_R2 8 351#define S_R1 4 352#define S_R0 0 353 354#define MODE_SVC 0x13 355#define I_BIT 0x80 356 357/* 358 * use bad_save_user_regs for abort/prefetch/undef/swi ... 359 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 360 */ 361 362 .macro bad_save_user_regs 363 sub sp, sp, #S_FRAME_SIZE 364 stmia sp, {r0 - r12} @ Calling r0-r12 365 ldr r2, IRQ_STACK_START_IN 366 ldmia r2, {r2 - r3} @ get pc, cpsr 367 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC 368 369 add r5, sp, #S_SP 370 mov r1, lr 371 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 372 mov r0, sp 373 .endm 374 375 .macro irq_save_user_regs 376 sub sp, sp, #S_FRAME_SIZE 377 stmia sp, {r0 - r12} @ Calling r0-r12 378 add r7, sp, #S_PC 379 stmdb r7, {sp, lr}^ @ Calling SP, LR 380 str lr, [r7, #0] @ Save calling PC 381 mrs r6, spsr 382 str r6, [r7, #4] @ Save CPSR 383 str r0, [r7, #8] @ Save OLD_R0 384 mov r0, sp 385 .endm 386 387 .macro irq_restore_user_regs 388 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 389 mov r0, r0 390 ldr lr, [sp, #S_PC] @ Get PC 391 add sp, sp, #S_FRAME_SIZE 392 /* return & move spsr_svc into cpsr */ 393 subs pc, lr, #4 394 .endm 395 396 .macro get_bad_stack 397 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 398 399 str lr, [r13] @ save caller lr / spsr 400 mrs lr, spsr 401 str lr, [r13, #4] 402 403 mov r13, #MODE_SVC @ prepare SVC-Mode 404 @ msr spsr_c, r13 405 msr spsr, r13 406 mov lr, pc 407 movs pc, lr 408 .endm 409 410 .macro get_irq_stack @ setup IRQ stack 411 ldr sp, IRQ_STACK_START 412 .endm 413 414 .macro get_fiq_stack @ setup FIQ stack 415 ldr sp, FIQ_STACK_START 416 .endm 417 418/* 419 * exception handlers 420 */ 421 .align 5 422undefined_instruction: 423 get_bad_stack 424 bad_save_user_regs 425 bl do_undefined_instruction 426 427 .align 5 428software_interrupt: 429 get_bad_stack 430 bad_save_user_regs 431 bl do_software_interrupt 432 433 .align 5 434prefetch_abort: 435 get_bad_stack 436 bad_save_user_regs 437 bl do_prefetch_abort 438 439 .align 5 440data_abort: 441 get_bad_stack 442 bad_save_user_regs 443 bl do_data_abort 444 445 .align 5 446not_used: 447 get_bad_stack 448 bad_save_user_regs 449 bl do_not_used 450 451#ifdef CONFIG_USE_IRQ 452 453 .align 5 454irq: 455 get_irq_stack 456 irq_save_user_regs 457 bl do_irq 458 irq_restore_user_regs 459 460 .align 5 461fiq: 462 get_fiq_stack 463 /* someone ought to write a more effiction fiq_save_user_regs */ 464 irq_save_user_regs 465 bl do_fiq 466 irq_restore_user_regs 467 468#else 469 470 .align 5 471irq: 472 get_bad_stack 473 bad_save_user_regs 474 bl do_irq 475 476 .align 5 477fiq: 478 get_bad_stack 479 bad_save_user_regs 480 bl do_fiq 481 482#endif 483