xref: /rk3399_rockchip-uboot/arch/arm/cpu/arm920t/ep93xx/cpu.c (revision 326ea986ac150acdc7656d57fca647db80b50158)
184ad6884SPeter Tyser /*
284ad6884SPeter Tyser  * Cirrus Logic EP93xx CPU-specific support.
384ad6884SPeter Tyser  *
484ad6884SPeter Tyser  * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
584ad6884SPeter Tyser  *
684ad6884SPeter Tyser  * Copyright (C) 2004, 2005
784ad6884SPeter Tyser  * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
884ad6884SPeter Tyser  *
9*1a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
1084ad6884SPeter Tyser  */
1184ad6884SPeter Tyser 
1284ad6884SPeter Tyser #include <common.h>
1384ad6884SPeter Tyser #include <asm/arch/ep93xx.h>
1484ad6884SPeter Tyser #include <asm/io.h>
1584ad6884SPeter Tyser 
1684ad6884SPeter Tyser /* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */
reset_cpu(ulong addr)1784ad6884SPeter Tyser extern void reset_cpu(ulong addr)
1884ad6884SPeter Tyser {
1984ad6884SPeter Tyser 	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
2084ad6884SPeter Tyser 	uint32_t value;
2184ad6884SPeter Tyser 
2284ad6884SPeter Tyser 	/* Unlock DeviceCfg and set SWRST */
2384ad6884SPeter Tyser 	writel(0xAA, &syscon->sysswlock);
2484ad6884SPeter Tyser 	value = readl(&syscon->devicecfg);
2584ad6884SPeter Tyser 	value |= SYSCON_DEVICECFG_SWRST;
2684ad6884SPeter Tyser 	writel(value, &syscon->devicecfg);
2784ad6884SPeter Tyser 
2884ad6884SPeter Tyser 	/* Unlock DeviceCfg and clear SWRST */
2984ad6884SPeter Tyser 	writel(0xAA, &syscon->sysswlock);
3084ad6884SPeter Tyser 	value = readl(&syscon->devicecfg);
3184ad6884SPeter Tyser 	value &= ~SYSCON_DEVICECFG_SWRST;
3284ad6884SPeter Tyser 	writel(value, &syscon->devicecfg);
3384ad6884SPeter Tyser 
3484ad6884SPeter Tyser 	/* Dying... */
3584ad6884SPeter Tyser 	while (1)
3684ad6884SPeter Tyser 		; /* noop */
3784ad6884SPeter Tyser }
38