1/* 2 * armboot - Startup Code for ARM720 CPU-core 3 * 4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26#include <asm-offsets.h> 27#include <config.h> 28#include <version.h> 29#include <asm/hardware.h> 30 31/* 32 ************************************************************************* 33 * 34 * Jump vector table as in table 3.1 in [1] 35 * 36 ************************************************************************* 37 */ 38 39 40.globl _start 41_start: b reset 42 ldr pc, _undefined_instruction 43 ldr pc, _software_interrupt 44 ldr pc, _prefetch_abort 45 ldr pc, _data_abort 46 ldr pc, _not_used 47 ldr pc, _irq 48 ldr pc, _fiq 49 50#ifdef CONFIG_SPL_BUILD 51_undefined_instruction: .word _undefined_instruction 52_software_interrupt: .word _software_interrupt 53_prefetch_abort: .word _prefetch_abort 54_data_abort: .word _data_abort 55_not_used: .word _not_used 56_irq: .word _irq 57_fiq: .word _fiq 58_pad: .word 0x12345678 /* now 16*4=64 */ 59#else 60_undefined_instruction: .word undefined_instruction 61_software_interrupt: .word software_interrupt 62_prefetch_abort: .word prefetch_abort 63_data_abort: .word data_abort 64_not_used: .word not_used 65_irq: .word irq 66_fiq: .word fiq 67_pad: .word 0x12345678 /* now 16*4=64 */ 68#endif /* CONFIG_SPL_BUILD */ 69 70 .balignl 16,0xdeadbeef 71 72 73/* 74 ************************************************************************* 75 * 76 * Startup Code (reset vector) 77 * 78 * do important init only if we don't start from RAM! 79 * relocate armboot to ram 80 * setup stack 81 * jump to second stage 82 * 83 ************************************************************************* 84 */ 85 86.globl _TEXT_BASE 87_TEXT_BASE: 88#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) 89 .word CONFIG_SPL_TEXT_BASE 90#else 91 .word CONFIG_SYS_TEXT_BASE 92#endif 93 94/* 95 * These are defined in the board-specific linker script. 96 * Subtracting _start from them lets the linker put their 97 * relative position in the executable instead of leaving 98 * them null. 99 */ 100.globl _bss_start_ofs 101_bss_start_ofs: 102 .word __bss_start - _start 103 104.globl _bss_end_ofs 105_bss_end_ofs: 106 .word __bss_end - _start 107 108.globl _end_ofs 109_end_ofs: 110 .word _end - _start 111 112#ifdef CONFIG_USE_IRQ 113/* IRQ stack memory (calculated at run-time) */ 114.globl IRQ_STACK_START 115IRQ_STACK_START: 116 .word 0x0badc0de 117 118/* IRQ stack memory (calculated at run-time) */ 119.globl FIQ_STACK_START 120FIQ_STACK_START: 121 .word 0x0badc0de 122#endif 123 124/* IRQ stack memory (calculated at run-time) + 8 bytes */ 125.globl IRQ_STACK_START_IN 126IRQ_STACK_START_IN: 127 .word 0x0badc0de 128 129/* 130 * the actual reset code 131 */ 132 133reset: 134 /* 135 * set the cpu to SVC32 mode 136 */ 137 mrs r0,cpsr 138 bic r0,r0,#0x1f 139 orr r0,r0,#0xd3 140 msr cpsr,r0 141 142 /* 143 * we do sys-critical inits only at reboot, 144 * not when booting from ram! 145 */ 146#ifndef CONFIG_SKIP_LOWLEVEL_INIT 147 bl cpu_init_crit 148#endif 149 150 bl _main 151 152/*------------------------------------------------------------------------------*/ 153 154#ifndef CONFIG_SPL_BUILD 155/* 156 * void relocate_code(addr_moni) 157 * 158 * This function relocates the monitor code. 159 */ 160 .globl relocate_code 161relocate_code: 162 mov r6, r0 /* save addr of destination */ 163 164 adr r0, _start 165 subs r9, r6, r0 /* r9 <- relocation offset */ 166 beq relocate_done /* skip relocation */ 167 mov r1, r6 /* r1 <- scratch for copy_loop */ 168 ldr r3, _image_copy_end_ofs 169 add r2, r0, r3 /* r2 <- source end address */ 170 171copy_loop: 172 ldmia r0!, {r10-r11} /* copy from source address [r0] */ 173 stmia r1!, {r10-r11} /* copy to target address [r1] */ 174 cmp r0, r2 /* until source end address [r2] */ 175 blo copy_loop 176 177 /* 178 * fix .rel.dyn relocations 179 */ 180 ldr r0, _TEXT_BASE /* r0 <- Text base */ 181 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 182 add r10, r10, r0 /* r10 <- sym table in FLASH */ 183 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 184 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 185 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 186 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 187fixloop: 188 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 189 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 190 ldr r1, [r2, #4] 191 and r7, r1, #0xff 192 cmp r7, #23 /* relative fixup? */ 193 beq fixrel 194 cmp r7, #2 /* absolute fixup? */ 195 beq fixabs 196 /* ignore unknown type of fixup */ 197 b fixnext 198fixabs: 199 /* absolute fix: set location to (offset) symbol value */ 200 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 201 add r1, r10, r1 /* r1 <- address of symbol in table */ 202 ldr r1, [r1, #4] /* r1 <- symbol value */ 203 add r1, r1, r9 /* r1 <- relocated sym addr */ 204 b fixnext 205fixrel: 206 /* relative fix: increase location by offset */ 207 ldr r1, [r0] 208 add r1, r1, r9 209fixnext: 210 str r1, [r0] 211 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 212 cmp r2, r3 213 blo fixloop 214 215relocate_done: 216 217 mov pc, lr 218 219_image_copy_end_ofs: 220 .word __image_copy_end - _start 221_rel_dyn_start_ofs: 222 .word __rel_dyn_start - _start 223_rel_dyn_end_ofs: 224 .word __rel_dyn_end - _start 225_dynsym_start_ofs: 226 .word __dynsym_start - _start 227 228#endif 229 230 .globl c_runtime_cpu_setup 231c_runtime_cpu_setup: 232 233 mov pc, lr 234 235/* 236 ************************************************************************* 237 * 238 * CPU_init_critical registers 239 * 240 * setup important registers 241 * setup memory timing 242 * 243 ************************************************************************* 244 */ 245 246#ifndef CONFIG_SKIP_LOWLEVEL_INIT 247cpu_init_crit: 248 249 mov ip, lr 250 /* 251 * before relocating, we have to setup RAM timing 252 * because memory timing is board-dependent, you will 253 * find a lowlevel_init.S in your board directory. 254 */ 255 bl lowlevel_init 256 mov lr, ip 257 258 mov pc, lr 259#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 260 261 262#ifndef CONFIG_SPL_BUILD 263/* 264 ************************************************************************* 265 * 266 * Interrupt handling 267 * 268 ************************************************************************* 269 */ 270 271@ 272@ IRQ stack frame. 273@ 274#define S_FRAME_SIZE 72 275 276#define S_OLD_R0 68 277#define S_PSR 64 278#define S_PC 60 279#define S_LR 56 280#define S_SP 52 281 282#define S_IP 48 283#define S_FP 44 284#define S_R10 40 285#define S_R9 36 286#define S_R8 32 287#define S_R7 28 288#define S_R6 24 289#define S_R5 20 290#define S_R4 16 291#define S_R3 12 292#define S_R2 8 293#define S_R1 4 294#define S_R0 0 295 296#define MODE_SVC 0x13 297#define I_BIT 0x80 298 299/* 300 * use bad_save_user_regs for abort/prefetch/undef/swi ... 301 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 302 */ 303 304 .macro bad_save_user_regs 305 sub sp, sp, #S_FRAME_SIZE 306 stmia sp, {r0 - r12} @ Calling r0-r12 307 add r8, sp, #S_PC 308 309 ldr r2, IRQ_STACK_START_IN 310 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 311 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC 312 313 add r5, sp, #S_SP 314 mov r1, lr 315 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r 316 mov r0, sp 317 .endm 318 319 .macro irq_save_user_regs 320 sub sp, sp, #S_FRAME_SIZE 321 stmia sp, {r0 - r12} @ Calling r0-r12 322 add r8, sp, #S_PC 323 stmdb r8, {sp, lr}^ @ Calling SP, LR 324 str lr, [r8, #0] @ Save calling PC 325 mrs r6, spsr 326 str r6, [r8, #4] @ Save CPSR 327 str r0, [r8, #8] @ Save OLD_R0 328 mov r0, sp 329 .endm 330 331 .macro irq_restore_user_regs 332 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 333 mov r0, r0 334 ldr lr, [sp, #S_PC] @ Get PC 335 add sp, sp, #S_FRAME_SIZE 336 subs pc, lr, #4 @ return & move spsr_svc into cpsr 337 .endm 338 339 .macro get_bad_stack 340 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 341 342 str lr, [r13] @ save caller lr / spsr 343 mrs lr, spsr 344 str lr, [r13, #4] 345 346 mov r13, #MODE_SVC @ prepare SVC-Mode 347 msr spsr_c, r13 348 mov lr, pc 349 movs pc, lr 350 .endm 351 352 .macro get_irq_stack @ setup IRQ stack 353 ldr sp, IRQ_STACK_START 354 .endm 355 356 .macro get_fiq_stack @ setup FIQ stack 357 ldr sp, FIQ_STACK_START 358 .endm 359 360/* 361 * exception handlers 362 */ 363 .align 5 364undefined_instruction: 365 get_bad_stack 366 bad_save_user_regs 367 bl do_undefined_instruction 368 369 .align 5 370software_interrupt: 371 get_bad_stack 372 bad_save_user_regs 373 bl do_software_interrupt 374 375 .align 5 376prefetch_abort: 377 get_bad_stack 378 bad_save_user_regs 379 bl do_prefetch_abort 380 381 .align 5 382data_abort: 383 get_bad_stack 384 bad_save_user_regs 385 bl do_data_abort 386 387 .align 5 388not_used: 389 get_bad_stack 390 bad_save_user_regs 391 bl do_not_used 392 393#ifdef CONFIG_USE_IRQ 394 395 .align 5 396irq: 397 get_irq_stack 398 irq_save_user_regs 399 bl do_irq 400 irq_restore_user_regs 401 402 .align 5 403fiq: 404 get_fiq_stack 405 /* someone ought to write a more effiction fiq_save_user_regs */ 406 irq_save_user_regs 407 bl do_fiq 408 irq_restore_user_regs 409 410#else 411 412 .align 5 413irq: 414 get_bad_stack 415 bad_save_user_regs 416 bl do_irq 417 418 .align 5 419fiq: 420 get_bad_stack 421 bad_save_user_regs 422 bl do_fiq 423 424#endif 425#endif /* CONFIG_SPL_BUILD */ 426