1/* 2 * armboot - Startup Code for ARM720 CPU-core 3 * 4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26#include <asm-offsets.h> 27#include <config.h> 28#include <version.h> 29#include <asm/hardware.h> 30 31/* 32 ************************************************************************* 33 * 34 * Jump vector table as in table 3.1 in [1] 35 * 36 ************************************************************************* 37 */ 38 39 40.globl _start 41_start: b reset 42 ldr pc, _undefined_instruction 43 ldr pc, _software_interrupt 44 ldr pc, _prefetch_abort 45 ldr pc, _data_abort 46 ldr pc, _not_used 47 ldr pc, _irq 48 ldr pc, _fiq 49 50#ifdef CONFIG_SPL_BUILD 51_undefined_instruction: .word _undefined_instruction 52_software_interrupt: .word _software_interrupt 53_prefetch_abort: .word _prefetch_abort 54_data_abort: .word _data_abort 55_not_used: .word _not_used 56_irq: .word _irq 57_fiq: .word _fiq 58_pad: .word 0x12345678 /* now 16*4=64 */ 59#else 60_undefined_instruction: .word undefined_instruction 61_software_interrupt: .word software_interrupt 62_prefetch_abort: .word prefetch_abort 63_data_abort: .word data_abort 64_not_used: .word not_used 65_irq: .word irq 66_fiq: .word fiq 67_pad: .word 0x12345678 /* now 16*4=64 */ 68#endif /* CONFIG_SPL_BUILD */ 69 70 .balignl 16,0xdeadbeef 71 72 73/* 74 ************************************************************************* 75 * 76 * Startup Code (reset vector) 77 * 78 * do important init only if we don't start from RAM! 79 * relocate armboot to ram 80 * setup stack 81 * jump to second stage 82 * 83 ************************************************************************* 84 */ 85 86.globl _TEXT_BASE 87_TEXT_BASE: 88#ifdef CONFIG_SPL_BUILD 89 .word CONFIG_SPL_TEXT_BASE 90#else 91 .word CONFIG_SYS_TEXT_BASE 92#endif 93 94/* 95 * These are defined in the board-specific linker script. 96 * Subtracting _start from them lets the linker put their 97 * relative position in the executable instead of leaving 98 * them null. 99 */ 100.globl _bss_start_ofs 101_bss_start_ofs: 102 .word __bss_start - _start 103 104.globl _bss_end_ofs 105_bss_end_ofs: 106 .word __bss_end__ - _start 107 108.globl _end_ofs 109_end_ofs: 110 .word _end - _start 111 112#ifdef CONFIG_USE_IRQ 113/* IRQ stack memory (calculated at run-time) */ 114.globl IRQ_STACK_START 115IRQ_STACK_START: 116 .word 0x0badc0de 117 118/* IRQ stack memory (calculated at run-time) */ 119.globl FIQ_STACK_START 120FIQ_STACK_START: 121 .word 0x0badc0de 122#endif 123 124/* IRQ stack memory (calculated at run-time) + 8 bytes */ 125.globl IRQ_STACK_START_IN 126IRQ_STACK_START_IN: 127 .word 0x0badc0de 128 129/* 130 * the actual reset code 131 */ 132 133reset: 134 /* 135 * set the cpu to SVC32 mode 136 */ 137 mrs r0,cpsr 138 bic r0,r0,#0x1f 139 orr r0,r0,#0xd3 140 msr cpsr,r0 141 142 /* 143 * we do sys-critical inits only at reboot, 144 * not when booting from ram! 145 */ 146#ifndef CONFIG_SKIP_LOWLEVEL_INIT 147 bl cpu_init_crit 148#endif 149 150/* Set stackpointer in internal RAM to call board_init_f */ 151call_board_init_f: 152 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 153 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 154 ldr r0,=0x00000000 155 bl board_init_f 156 157/*------------------------------------------------------------------------------*/ 158 159/* 160 * void relocate_code (addr_sp, gd, addr_moni) 161 * 162 * This "function" does not return, instead it continues in RAM 163 * after relocating the monitor code. 164 * 165 */ 166 .globl relocate_code 167relocate_code: 168 mov r4, r0 /* save addr_sp */ 169 mov r5, r1 /* save addr of gd */ 170 mov r6, r2 /* save addr of destination */ 171 172 /* Set up the stack */ 173stack_setup: 174 mov sp, r4 175 176 adr r0, _start 177 cmp r0, r6 178 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ 179 beq clear_bss /* skip relocation */ 180 mov r1, r6 /* r1 <- scratch for copy_loop */ 181 ldr r3, _bss_start_ofs 182 add r2, r0, r3 /* r2 <- source end address */ 183 184copy_loop: 185 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 186 stmia r1!, {r9-r10} /* copy to target address [r1] */ 187 cmp r0, r2 /* until source end address [r2] */ 188 blo copy_loop 189 190#ifndef CONFIG_SPL_BUILD 191 /* 192 * fix .rel.dyn relocations 193 */ 194 ldr r0, _TEXT_BASE /* r0 <- Text base */ 195 sub r9, r6, r0 /* r9 <- relocation offset */ 196 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 197 add r10, r10, r0 /* r10 <- sym table in FLASH */ 198 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 199 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 200 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 201 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 202fixloop: 203 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 204 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 205 ldr r1, [r2, #4] 206 and r7, r1, #0xff 207 cmp r7, #23 /* relative fixup? */ 208 beq fixrel 209 cmp r7, #2 /* absolute fixup? */ 210 beq fixabs 211 /* ignore unknown type of fixup */ 212 b fixnext 213fixabs: 214 /* absolute fix: set location to (offset) symbol value */ 215 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 216 add r1, r10, r1 /* r1 <- address of symbol in table */ 217 ldr r1, [r1, #4] /* r1 <- symbol value */ 218 add r1, r1, r9 /* r1 <- relocated sym addr */ 219 b fixnext 220fixrel: 221 /* relative fix: increase location by offset */ 222 ldr r1, [r0] 223 add r1, r1, r9 224fixnext: 225 str r1, [r0] 226 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 227 cmp r2, r3 228 blo fixloop 229#endif 230 231clear_bss: 232#ifndef CONFIG_SPL_BUILD 233 ldr r0, _bss_start_ofs 234 ldr r1, _bss_end_ofs 235 mov r4, r6 /* reloc addr */ 236 add r0, r0, r4 237 add r1, r1, r4 238 mov r2, #0x00000000 /* clear */ 239 240clbss_l:cmp r0, r1 /* clear loop... */ 241 bhs clbss_e /* if reached end of bss, exit */ 242 str r2, [r0] 243 add r0, r0, #4 244 b clbss_l 245clbss_e: 246 247 bl coloured_LED_init 248 bl red_led_on 249#endif 250 251/* 252 * We are done. Do not return, instead branch to second part of board 253 * initialization, now running from RAM. 254 */ 255 ldr r0, _board_init_r_ofs 256 adr r1, _start 257 add lr, r0, r1 258 add lr, lr, r9 259 /* setup parameters for board_init_r */ 260 mov r0, r5 /* gd_t */ 261 mov r1, r6 /* dest_addr */ 262 /* jump to it ... */ 263 mov pc, lr 264 265_board_init_r_ofs: 266 .word board_init_r - _start 267 268_rel_dyn_start_ofs: 269 .word __rel_dyn_start - _start 270_rel_dyn_end_ofs: 271 .word __rel_dyn_end - _start 272_dynsym_start_ofs: 273 .word __dynsym_start - _start 274 275/* 276 ************************************************************************* 277 * 278 * CPU_init_critical registers 279 * 280 * setup important registers 281 * setup memory timing 282 * 283 ************************************************************************* 284 */ 285 286cpu_init_crit: 287#if defined(CONFIG_NETARM) 288 /* 289 * prior to software reset : need to set pin PORTC4 to be *HRESET 290 */ 291 ldr r0, =NETARM_GEN_MODULE_BASE 292 ldr r1, =(NETARM_GEN_PORT_MODE(0x10) | \ 293 NETARM_GEN_PORT_DIR(0x10)) 294 str r1, [r0, #+NETARM_GEN_PORTC] 295 /* 296 * software reset : see HW Ref. Guide 8.2.4 : Software Service register 297 * for an explanation of this process 298 */ 299 ldr r0, =NETARM_GEN_MODULE_BASE 300 ldr r1, =NETARM_GEN_SW_SVC_RESETA 301 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] 302 ldr r1, =NETARM_GEN_SW_SVC_RESETB 303 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] 304 ldr r1, =NETARM_GEN_SW_SVC_RESETA 305 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] 306 ldr r1, =NETARM_GEN_SW_SVC_RESETB 307 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] 308 /* 309 * setup PLL and System Config 310 */ 311 ldr r0, =NETARM_GEN_MODULE_BASE 312 313 ldr r1, =( NETARM_GEN_SYS_CFG_LENDIAN | \ 314 NETARM_GEN_SYS_CFG_BUSFULL | \ 315 NETARM_GEN_SYS_CFG_USER_EN | \ 316 NETARM_GEN_SYS_CFG_ALIGN_ABORT | \ 317 NETARM_GEN_SYS_CFG_BUSARB_INT | \ 318 NETARM_GEN_SYS_CFG_BUSMON_EN ) 319 320 str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL] 321 322#ifndef CONFIG_NETARM_PLL_BYPASS 323 ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \ 324 NETARM_GEN_PLL_CTL_POLTST_DEF | \ 325 NETARM_GEN_PLL_CTL_INDIV(1) | \ 326 NETARM_GEN_PLL_CTL_ICP_DEF | \ 327 NETARM_GEN_PLL_CTL_OUTDIV(2) ) 328 str r1, [r0, #+NETARM_GEN_PLL_CONTROL] 329#endif 330 331 /* 332 * mask all IRQs by clearing all bits in the INTMRs 333 */ 334 mov r1, #0 335 ldr r0, =NETARM_GEN_MODULE_BASE 336 str r1, [r0, #+NETARM_GEN_INTR_ENABLE] 337 338#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) 339 /* No specific initialisation for IntegratorAP/CM720T as yet */ 340#elif defined(CONFIG_TEGRA) 341 /* No cpu_init_crit for tegra as yet */ 342#else 343#error No cpu_init_crit() defined for current CPU type 344#endif 345 346#ifdef CONFIG_ARM7_REVD 347 /* set clock speed */ 348 /* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */ 349 /* !!! not doing DRAM refresh properly! */ 350 ldr r0, SYSCON3 351 ldr r1, [r0] 352 bic r1, r1, #CLKCTL 353 orr r1, r1, #CLKCTL_36 354 str r1, [r0] 355#endif 356 357#if !defined(CONFIG_TEGRA) 358 mov ip, lr 359 /* 360 * before relocating, we have to setup RAM timing 361 * because memory timing is board-dependent, you will 362 * find a lowlevel_init.S in your board directory. 363 */ 364 bl lowlevel_init 365 mov lr, ip 366#endif 367 368 mov pc, lr 369 370 371#ifndef CONFIG_SPL_BUILD 372/* 373 ************************************************************************* 374 * 375 * Interrupt handling 376 * 377 ************************************************************************* 378 */ 379 380@ 381@ IRQ stack frame. 382@ 383#define S_FRAME_SIZE 72 384 385#define S_OLD_R0 68 386#define S_PSR 64 387#define S_PC 60 388#define S_LR 56 389#define S_SP 52 390 391#define S_IP 48 392#define S_FP 44 393#define S_R10 40 394#define S_R9 36 395#define S_R8 32 396#define S_R7 28 397#define S_R6 24 398#define S_R5 20 399#define S_R4 16 400#define S_R3 12 401#define S_R2 8 402#define S_R1 4 403#define S_R0 0 404 405#define MODE_SVC 0x13 406#define I_BIT 0x80 407 408/* 409 * use bad_save_user_regs for abort/prefetch/undef/swi ... 410 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 411 */ 412 413 .macro bad_save_user_regs 414 sub sp, sp, #S_FRAME_SIZE 415 stmia sp, {r0 - r12} @ Calling r0-r12 416 add r8, sp, #S_PC 417 418 ldr r2, IRQ_STACK_START_IN 419 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 420 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC 421 422 add r5, sp, #S_SP 423 mov r1, lr 424 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r 425 mov r0, sp 426 .endm 427 428 .macro irq_save_user_regs 429 sub sp, sp, #S_FRAME_SIZE 430 stmia sp, {r0 - r12} @ Calling r0-r12 431 add r8, sp, #S_PC 432 stmdb r8, {sp, lr}^ @ Calling SP, LR 433 str lr, [r8, #0] @ Save calling PC 434 mrs r6, spsr 435 str r6, [r8, #4] @ Save CPSR 436 str r0, [r8, #8] @ Save OLD_R0 437 mov r0, sp 438 .endm 439 440 .macro irq_restore_user_regs 441 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 442 mov r0, r0 443 ldr lr, [sp, #S_PC] @ Get PC 444 add sp, sp, #S_FRAME_SIZE 445 subs pc, lr, #4 @ return & move spsr_svc into cpsr 446 .endm 447 448 .macro get_bad_stack 449 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 450 451 str lr, [r13] @ save caller lr / spsr 452 mrs lr, spsr 453 str lr, [r13, #4] 454 455 mov r13, #MODE_SVC @ prepare SVC-Mode 456 msr spsr_c, r13 457 mov lr, pc 458 movs pc, lr 459 .endm 460 461 .macro get_irq_stack @ setup IRQ stack 462 ldr sp, IRQ_STACK_START 463 .endm 464 465 .macro get_fiq_stack @ setup FIQ stack 466 ldr sp, FIQ_STACK_START 467 .endm 468 469/* 470 * exception handlers 471 */ 472 .align 5 473undefined_instruction: 474 get_bad_stack 475 bad_save_user_regs 476 bl do_undefined_instruction 477 478 .align 5 479software_interrupt: 480 get_bad_stack 481 bad_save_user_regs 482 bl do_software_interrupt 483 484 .align 5 485prefetch_abort: 486 get_bad_stack 487 bad_save_user_regs 488 bl do_prefetch_abort 489 490 .align 5 491data_abort: 492 get_bad_stack 493 bad_save_user_regs 494 bl do_data_abort 495 496 .align 5 497not_used: 498 get_bad_stack 499 bad_save_user_regs 500 bl do_not_used 501 502#ifdef CONFIG_USE_IRQ 503 504 .align 5 505irq: 506 get_irq_stack 507 irq_save_user_regs 508 bl do_irq 509 irq_restore_user_regs 510 511 .align 5 512fiq: 513 get_fiq_stack 514 /* someone ought to write a more effiction fiq_save_user_regs */ 515 irq_save_user_regs 516 bl do_fiq 517 irq_restore_user_regs 518 519#else 520 521 .align 5 522irq: 523 get_bad_stack 524 bad_save_user_regs 525 bl do_irq 526 527 .align 5 528fiq: 529 get_bad_stack 530 bad_save_user_regs 531 bl do_fiq 532 533#endif 534#endif /* CONFIG_SPL_BUILD */ 535 536#if defined(CONFIG_NETARM) 537 .align 5 538.globl reset_cpu 539reset_cpu: 540 ldr r1, =NETARM_MEM_MODULE_BASE 541 ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR] 542 ldr r1, =0xFFFFF000 543 and r0, r1, r0 544 ldr r1, =(relocate-CONFIG_SYS_TEXT_BASE) 545 add r0, r1, r0 546 ldr r4, =NETARM_GEN_MODULE_BASE 547 ldr r1, =NETARM_GEN_SW_SVC_RESETA 548 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] 549 ldr r1, =NETARM_GEN_SW_SVC_RESETB 550 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] 551 ldr r1, =NETARM_GEN_SW_SVC_RESETA 552 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] 553 ldr r1, =NETARM_GEN_SW_SVC_RESETB 554 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] 555 mov pc, r0 556#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) 557 /* No specific reset actions for IntegratorAP/CM720T as yet */ 558#elif defined(CONFIG_TEGRA) 559 /* No specific reset actions for tegra as yet */ 560#else 561#error No reset_cpu() defined for current CPU type 562#endif 563