1/* 2 * armboot - Startup Code for ARM1176 CPU-core 3 * 4 * Copyright (c) 2007 Samsung Electronics 5 * 6 * Copyright (C) 2008 7 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 * 27 * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com) 28 * 2007-09-21 - Added MoviNAND and OneNAND boot codes by 29 * jsgood (jsgood.yang@samsung.com) 30 * Base codes by scsuh (sc.suh) 31 */ 32 33#include <asm-offsets.h> 34#include <config.h> 35#include <version.h> 36 37#ifndef CONFIG_SYS_PHY_UBOOT_BASE 38#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE 39#endif 40 41/* 42 ************************************************************************* 43 * 44 * Jump vector table as in table 3.1 in [1] 45 * 46 ************************************************************************* 47 */ 48 49.globl _start 50_start: b reset 51#ifndef CONFIG_SPL_BUILD 52 ldr pc, _undefined_instruction 53 ldr pc, _software_interrupt 54 ldr pc, _prefetch_abort 55 ldr pc, _data_abort 56 ldr pc, _not_used 57 ldr pc, _irq 58 ldr pc, _fiq 59 60_undefined_instruction: 61 .word undefined_instruction 62_software_interrupt: 63 .word software_interrupt 64_prefetch_abort: 65 .word prefetch_abort 66_data_abort: 67 .word data_abort 68_not_used: 69 .word not_used 70_irq: 71 .word irq 72_fiq: 73 .word fiq 74_pad: 75 .word 0x12345678 /* now 16*4=64 */ 76#else 77 . = _start + 64 78#endif 79 80.global _end_vect 81_end_vect: 82 .balignl 16,0xdeadbeef 83/* 84 ************************************************************************* 85 * 86 * Startup Code (reset vector) 87 * 88 * do important init only if we don't start from memory! 89 * setup Memory and board specific bits prior to relocation. 90 * relocate armboot to ram 91 * setup stack 92 * 93 ************************************************************************* 94 */ 95 96.globl _TEXT_BASE 97_TEXT_BASE: 98#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) 99 .word CONFIG_SPL_TEXT_BASE 100#else 101 .word CONFIG_SYS_TEXT_BASE 102#endif 103 104/* 105 * These are defined in the board-specific linker script. 106 * Subtracting _start from them lets the linker put their 107 * relative position in the executable instead of leaving 108 * them null. 109 */ 110 111.globl _bss_start_ofs 112_bss_start_ofs: 113 .word __bss_start - _start 114 115.globl _bss_end_ofs 116_bss_end_ofs: 117 .word __bss_end - _start 118 119.globl _end_ofs 120_end_ofs: 121 .word _end - _start 122 123/* IRQ stack memory (calculated at run-time) + 8 bytes */ 124.globl IRQ_STACK_START_IN 125IRQ_STACK_START_IN: 126 .word 0x0badc0de 127 128/* 129 * the actual reset code 130 */ 131 132reset: 133 /* 134 * set the cpu to SVC32 mode 135 */ 136 mrs r0, cpsr 137 bic r0, r0, #0x3f 138 orr r0, r0, #0xd3 139 msr cpsr, r0 140 141/* 142 ************************************************************************* 143 * 144 * CPU_init_critical registers 145 * 146 * setup important registers 147 * setup memory timing 148 * 149 ************************************************************************* 150 */ 151 /* 152 * we do sys-critical inits only at reboot, 153 * not when booting from ram! 154 */ 155cpu_init_crit: 156 /* 157 * When booting from NAND - it has definitely been a reset, so, no need 158 * to flush caches and disable the MMU 159 */ 160#ifndef CONFIG_SPL_BUILD 161 /* 162 * flush v4 I/D caches 163 */ 164 mov r0, #0 165 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 166 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 167 168 /* 169 * disable MMU stuff and caches 170 */ 171 mrc p15, 0, r0, c1, c0, 0 172 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 173 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 174 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 175 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 176 177 /* Prepare to disable the MMU */ 178 adr r2, mmu_disable_phys 179 sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE) 180 b mmu_disable 181 182 .align 5 183 /* Run in a single cache-line */ 184mmu_disable: 185 mcr p15, 0, r0, c1, c0, 0 186 nop 187 nop 188 mov pc, r2 189mmu_disable_phys: 190 191#ifdef CONFIG_DISABLE_TCM 192 /* 193 * Disable the TCMs 194 */ 195 mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */ 196 cmp r0, #0 197 beq skip_tcmdisable 198 mov r1, #0 199 mov r2, #1 200 tst r0, r2 201 mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/ 202 tst r0, r2, LSL #16 203 mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/ 204skip_tcmdisable: 205#endif 206#endif 207 208#ifdef CONFIG_PERIPORT_REMAP 209 /* Peri port setup */ 210 ldr r0, =CONFIG_PERIPORT_BASE 211 orr r0, r0, #CONFIG_PERIPORT_SIZE 212 mcr p15,0,r0,c15,c2,4 213#endif 214 215 /* 216 * Go setup Memory and board specific bits prior to relocation. 217 */ 218 bl lowlevel_init /* go setup pll,mux,memory */ 219 220 bl _main 221 222/*------------------------------------------------------------------------------*/ 223 224#ifndef CONFIG_SPL_BUILD 225/* 226 * void relocate_code(addr_moni) 227 * 228 * This function relocates the monitor code. 229 */ 230 .globl relocate_code 231relocate_code: 232 mov r6, r0 /* save addr of destination */ 233 234 adr r0, _start 235 subs r9, r6, r0 /* r9 <- relocation offset */ 236 beq relocate_done /* skip relocation */ 237 mov r1, r6 /* r1 <- scratch for copy_loop */ 238 ldr r3, _image_copy_end_ofs 239 add r2, r0, r3 /* r2 <- source end address */ 240 241copy_loop: 242 ldmia r0!, {r10-r11} /* copy from source address [r0] */ 243 stmia r1!, {r10-r11} /* copy to target address [r1] */ 244 cmp r0, r2 /* until source end address [r2] */ 245 blo copy_loop 246 247 /* 248 * fix .rel.dyn relocations 249 */ 250 ldr r0, _TEXT_BASE /* r0 <- Text base */ 251 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 252 add r10, r10, r0 /* r10 <- sym table in FLASH */ 253 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 254 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 255 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 256 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 257fixloop: 258 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 259 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 260 ldr r1, [r2, #4] 261 and r7, r1, #0xff 262 cmp r7, #23 /* relative fixup? */ 263 beq fixrel 264 cmp r7, #2 /* absolute fixup? */ 265 beq fixabs 266 /* ignore unknown type of fixup */ 267 b fixnext 268fixabs: 269 /* absolute fix: set location to (offset) symbol value */ 270 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 271 add r1, r10, r1 /* r1 <- address of symbol in table */ 272 ldr r1, [r1, #4] /* r1 <- symbol value */ 273 add r1, r1, r9 /* r1 <- relocated sym addr */ 274 b fixnext 275fixrel: 276 /* relative fix: increase location by offset */ 277 ldr r1, [r0] 278 add r1, r1, r9 279fixnext: 280 str r1, [r0] 281 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 282 cmp r2, r3 283 blo fixloop 284 285relocate_done: 286 287 bx lr 288 289_image_copy_end_ofs: 290 .word __image_copy_end - _start 291_rel_dyn_start_ofs: 292 .word __rel_dyn_start - _start 293_rel_dyn_end_ofs: 294 .word __rel_dyn_end - _start 295_dynsym_start_ofs: 296 .word __dynsym_start - _start 297 298#endif 299 300 .globl c_runtime_cpu_setup 301c_runtime_cpu_setup: 302 303 mov pc, lr 304 305#ifndef CONFIG_SPL_BUILD 306/* 307 ************************************************************************* 308 * 309 * Interrupt handling 310 * 311 ************************************************************************* 312 */ 313@ 314@ IRQ stack frame. 315@ 316#define S_FRAME_SIZE 72 317 318#define S_OLD_R0 68 319#define S_PSR 64 320#define S_PC 60 321#define S_LR 56 322#define S_SP 52 323 324#define S_IP 48 325#define S_FP 44 326#define S_R10 40 327#define S_R9 36 328#define S_R8 32 329#define S_R7 28 330#define S_R6 24 331#define S_R5 20 332#define S_R4 16 333#define S_R3 12 334#define S_R2 8 335#define S_R1 4 336#define S_R0 0 337 338#define MODE_SVC 0x13 339#define I_BIT 0x80 340 341/* 342 * use bad_save_user_regs for abort/prefetch/undef/swi ... 343 */ 344 345 .macro bad_save_user_regs 346 /* carve out a frame on current user stack */ 347 sub sp, sp, #S_FRAME_SIZE 348 /* Save user registers (now in svc mode) r0-r12 */ 349 stmia sp, {r0 - r12} 350 351 ldr r2, IRQ_STACK_START_IN 352 /* get values for "aborted" pc and cpsr (into parm regs) */ 353 ldmia r2, {r2 - r3} 354 /* grab pointer to old stack */ 355 add r0, sp, #S_FRAME_SIZE 356 357 add r5, sp, #S_SP 358 mov r1, lr 359 /* save sp_SVC, lr_SVC, pc, cpsr */ 360 stmia r5, {r0 - r3} 361 /* save current stack into r0 (param register) */ 362 mov r0, sp 363 .endm 364 365 .macro get_bad_stack 366 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 367 368 /* save caller lr in position 0 of saved stack */ 369 str lr, [r13] 370 /* get the spsr */ 371 mrs lr, spsr 372 /* save spsr in position 1 of saved stack */ 373 str lr, [r13, #4] 374 375 /* prepare SVC-Mode */ 376 mov r13, #MODE_SVC 377 @ msr spsr_c, r13 378 /* switch modes, make sure moves will execute */ 379 msr spsr, r13 380 /* capture return pc */ 381 mov lr, pc 382 /* jump to next instruction & switch modes. */ 383 movs pc, lr 384 .endm 385 386 .macro get_bad_stack_swi 387 /* space on current stack for scratch reg. */ 388 sub r13, r13, #4 389 /* save R0's value. */ 390 str r0, [r13] 391 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 392 /* save caller lr in position 0 of saved stack */ 393 str lr, [r0] 394 /* get the spsr */ 395 mrs lr, spsr 396 /* save spsr in position 1 of saved stack */ 397 str lr, [r0, #4] 398 /* restore lr */ 399 ldr lr, [r0] 400 /* restore r0 */ 401 ldr r0, [r13] 402 /* pop stack entry */ 403 add r13, r13, #4 404 .endm 405 406/* 407 * exception handlers 408 */ 409 .align 5 410undefined_instruction: 411 get_bad_stack 412 bad_save_user_regs 413 bl do_undefined_instruction 414 415 .align 5 416software_interrupt: 417 get_bad_stack_swi 418 bad_save_user_regs 419 bl do_software_interrupt 420 421 .align 5 422prefetch_abort: 423 get_bad_stack 424 bad_save_user_regs 425 bl do_prefetch_abort 426 427 .align 5 428data_abort: 429 get_bad_stack 430 bad_save_user_regs 431 bl do_data_abort 432 433 .align 5 434not_used: 435 get_bad_stack 436 bad_save_user_regs 437 bl do_not_used 438 439 .align 5 440irq: 441 get_bad_stack 442 bad_save_user_regs 443 bl do_irq 444 445 .align 5 446fiq: 447 get_bad_stack 448 bad_save_user_regs 449 bl do_fiq 450#endif /* CONFIG_SPL_BUILD */ 451