1/* 2 * armboot - Startup Code for ARM1176 CPU-core 3 * 4 * Copyright (c) 2007 Samsung Electronics 5 * 6 * Copyright (C) 2008 7 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 * 27 * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com) 28 * 2007-09-21 - Added MoviNAND and OneNAND boot codes by 29 * jsgood (jsgood.yang@samsung.com) 30 * Base codes by scsuh (sc.suh) 31 */ 32 33#include <asm-offsets.h> 34#include <config.h> 35#include <version.h> 36#ifdef CONFIG_ENABLE_MMU 37#include <asm/proc/domain.h> 38#endif 39 40#if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE) 41#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE 42#endif 43 44/* 45 ************************************************************************* 46 * 47 * Jump vector table as in table 3.1 in [1] 48 * 49 ************************************************************************* 50 */ 51 52.globl _start 53_start: b reset 54#ifndef CONFIG_NAND_SPL 55 ldr pc, _undefined_instruction 56 ldr pc, _software_interrupt 57 ldr pc, _prefetch_abort 58 ldr pc, _data_abort 59 ldr pc, _not_used 60 ldr pc, _irq 61 ldr pc, _fiq 62 63_undefined_instruction: 64 .word undefined_instruction 65_software_interrupt: 66 .word software_interrupt 67_prefetch_abort: 68 .word prefetch_abort 69_data_abort: 70 .word data_abort 71_not_used: 72 .word not_used 73_irq: 74 .word irq 75_fiq: 76 .word fiq 77_pad: 78 .word 0x12345678 /* now 16*4=64 */ 79#else 80 . = _start + 64 81#endif 82 83.global _end_vect 84_end_vect: 85 .balignl 16,0xdeadbeef 86/* 87 ************************************************************************* 88 * 89 * Startup Code (reset vector) 90 * 91 * do important init only if we don't start from memory! 92 * setup Memory and board specific bits prior to relocation. 93 * relocate armboot to ram 94 * setup stack 95 * 96 ************************************************************************* 97 */ 98 99.globl _TEXT_BASE 100_TEXT_BASE: 101#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */ 102 .word CONFIG_SYS_TEXT_BASE 103#else 104#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) 105 .word CONFIG_SPL_TEXT_BASE 106#else 107 .word CONFIG_SYS_TEXT_BASE 108#endif 109#endif 110 111/* 112 * Below variable is very important because we use MMU in U-Boot. 113 * Without it, we cannot run code correctly before MMU is ON. 114 * by scsuh. 115 */ 116_TEXT_PHY_BASE: 117 .word CONFIG_SYS_PHY_UBOOT_BASE 118 119/* 120 * These are defined in the board-specific linker script. 121 * Subtracting _start from them lets the linker put their 122 * relative position in the executable instead of leaving 123 * them null. 124 */ 125 126.globl _bss_start_ofs 127_bss_start_ofs: 128 .word __bss_start - _start 129 130.globl _image_copy_end_ofs 131_image_copy_end_ofs: 132 .word __image_copy_end - _start 133 134.globl _bss_end_ofs 135_bss_end_ofs: 136 .word __bss_end - _start 137 138.globl _end_ofs 139_end_ofs: 140 .word _end - _start 141 142/* IRQ stack memory (calculated at run-time) + 8 bytes */ 143.globl IRQ_STACK_START_IN 144IRQ_STACK_START_IN: 145 .word 0x0badc0de 146 147/* 148 * the actual reset code 149 */ 150 151reset: 152 /* 153 * set the cpu to SVC32 mode 154 */ 155 mrs r0, cpsr 156 bic r0, r0, #0x3f 157 orr r0, r0, #0xd3 158 msr cpsr, r0 159 160/* 161 ************************************************************************* 162 * 163 * CPU_init_critical registers 164 * 165 * setup important registers 166 * setup memory timing 167 * 168 ************************************************************************* 169 */ 170 /* 171 * we do sys-critical inits only at reboot, 172 * not when booting from ram! 173 */ 174cpu_init_crit: 175 /* 176 * When booting from NAND - it has definitely been a reset, so, no need 177 * to flush caches and disable the MMU 178 */ 179#ifndef CONFIG_NAND_SPL 180 /* 181 * flush v4 I/D caches 182 */ 183 mov r0, #0 184 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 185 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 186 187 /* 188 * disable MMU stuff and caches 189 */ 190 mrc p15, 0, r0, c1, c0, 0 191 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 192 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 193 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 194 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 195 196 /* Prepare to disable the MMU */ 197 adr r2, mmu_disable_phys 198 sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE) 199 b mmu_disable 200 201 .align 5 202 /* Run in a single cache-line */ 203mmu_disable: 204 mcr p15, 0, r0, c1, c0, 0 205 nop 206 nop 207 mov pc, r2 208mmu_disable_phys: 209 210#ifdef CONFIG_DISABLE_TCM 211 /* 212 * Disable the TCMs 213 */ 214 mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */ 215 cmp r0, #0 216 beq skip_tcmdisable 217 mov r1, #0 218 mov r2, #1 219 tst r0, r2 220 mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/ 221 tst r0, r2, LSL #16 222 mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/ 223skip_tcmdisable: 224#endif 225#endif 226 227#ifdef CONFIG_PERIPORT_REMAP 228 /* Peri port setup */ 229 ldr r0, =CONFIG_PERIPORT_BASE 230 orr r0, r0, #CONFIG_PERIPORT_SIZE 231 mcr p15,0,r0,c15,c2,4 232#endif 233 234 /* 235 * Go setup Memory and board specific bits prior to relocation. 236 */ 237 bl lowlevel_init /* go setup pll,mux,memory */ 238 239 bl _main 240 241/*------------------------------------------------------------------------------*/ 242 243/* 244 * void relocate_code(addr_moni) 245 * 246 * This function relocates the monitor code. 247 */ 248 .globl relocate_code 249relocate_code: 250 mov r6, r0 /* save addr of destination */ 251 252 adr r0, _start 253 subs r9, r6, r0 /* r9 <- relocation offset */ 254 beq relocate_done /* skip relocation */ 255 mov r1, r6 /* r1 <- scratch for copy_loop */ 256 ldr r3, _image_copy_end_ofs 257 add r2, r0, r3 /* r2 <- source end address */ 258 259copy_loop: 260 ldmia r0!, {r10-r11} /* copy from source address [r0] */ 261 stmia r1!, {r10-r11} /* copy to target address [r1] */ 262 cmp r0, r2 /* until source end address [r2] */ 263 blo copy_loop 264 265#ifndef CONFIG_SPL_BUILD 266 /* 267 * fix .rel.dyn relocations 268 */ 269 ldr r0, _TEXT_BASE /* r0 <- Text base */ 270 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 271 add r10, r10, r0 /* r10 <- sym table in FLASH */ 272 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 273 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 274 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 275 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 276fixloop: 277 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 278 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 279 ldr r1, [r2, #4] 280 and r7, r1, #0xff 281 cmp r7, #23 /* relative fixup? */ 282 beq fixrel 283 cmp r7, #2 /* absolute fixup? */ 284 beq fixabs 285 /* ignore unknown type of fixup */ 286 b fixnext 287fixabs: 288 /* absolute fix: set location to (offset) symbol value */ 289 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 290 add r1, r10, r1 /* r1 <- address of symbol in table */ 291 ldr r1, [r1, #4] /* r1 <- symbol value */ 292 add r1, r1, r9 /* r1 <- relocated sym addr */ 293 b fixnext 294fixrel: 295 /* relative fix: increase location by offset */ 296 ldr r1, [r0] 297 add r1, r1, r9 298fixnext: 299 str r1, [r0] 300 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 301 cmp r2, r3 302 blo fixloop 303#endif 304 305#ifdef CONFIG_ENABLE_MMU 306enable_mmu: 307 /* enable domain access */ 308 ldr r5, =0x0000ffff 309 mcr p15, 0, r5, c3, c0, 0 /* load domain access register */ 310 311 /* Set the TTB register */ 312 ldr r0, _mmu_table_base 313 ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE 314 ldr r2, =0xfff00000 315 bic r0, r0, r2 316 orr r1, r0, r1 317 mcr p15, 0, r1, c2, c0, 0 318 319 /* Enable the MMU */ 320 mrc p15, 0, r0, c1, c0, 0 321 orr r0, r0, #1 /* Set CR_M to enable MMU */ 322 323 /* Prepare to enable the MMU */ 324 adr r1, skip_hw_init 325 and r1, r1, #0x3fc 326 ldr r2, _TEXT_BASE 327 ldr r3, =0xfff00000 328 and r2, r2, r3 329 orr r2, r2, r1 330 b mmu_enable 331 332 .align 5 333 /* Run in a single cache-line */ 334mmu_enable: 335 336 mcr p15, 0, r0, c1, c0, 0 337 nop 338 nop 339 mov pc, r2 340skip_hw_init: 341#endif 342 343relocate_done: 344 345 bx lr 346 347_rel_dyn_start_ofs: 348 .word __rel_dyn_start - _start 349_rel_dyn_end_ofs: 350 .word __rel_dyn_end - _start 351_dynsym_start_ofs: 352 .word __dynsym_start - _start 353 354#ifdef CONFIG_ENABLE_MMU 355_mmu_table_base: 356 .word mmu_table 357#endif 358 359 .globl c_runtime_cpu_setup 360c_runtime_cpu_setup: 361 362 mov pc, lr 363 364#ifndef CONFIG_NAND_SPL 365/* 366 * we assume that cache operation is done before. (eg. cleanup_before_linux()) 367 * actually, we don't need to do anything about cache if not use d-cache in 368 * U-Boot. So, in this function we clean only MMU. by scsuh 369 * 370 * void theLastJump(void *kernel, int arch_num, uint boot_params); 371 */ 372#ifdef CONFIG_ENABLE_MMU 373 .globl theLastJump 374theLastJump: 375 mov r9, r0 376 ldr r3, =0xfff00000 377 ldr r4, _TEXT_PHY_BASE 378 adr r5, phy_last_jump 379 bic r5, r5, r3 380 orr r5, r5, r4 381 mov pc, r5 382phy_last_jump: 383 /* 384 * disable MMU stuff 385 */ 386 mrc p15, 0, r0, c1, c0, 0 387 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ 388 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ 389 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ 390 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ 391 mcr p15, 0, r0, c1, c0, 0 392 393 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 394 395 mov r0, #0 396 mov pc, r9 397#endif 398 399 400/* 401 ************************************************************************* 402 * 403 * Interrupt handling 404 * 405 ************************************************************************* 406 */ 407@ 408@ IRQ stack frame. 409@ 410#define S_FRAME_SIZE 72 411 412#define S_OLD_R0 68 413#define S_PSR 64 414#define S_PC 60 415#define S_LR 56 416#define S_SP 52 417 418#define S_IP 48 419#define S_FP 44 420#define S_R10 40 421#define S_R9 36 422#define S_R8 32 423#define S_R7 28 424#define S_R6 24 425#define S_R5 20 426#define S_R4 16 427#define S_R3 12 428#define S_R2 8 429#define S_R1 4 430#define S_R0 0 431 432#define MODE_SVC 0x13 433#define I_BIT 0x80 434 435/* 436 * use bad_save_user_regs for abort/prefetch/undef/swi ... 437 */ 438 439 .macro bad_save_user_regs 440 /* carve out a frame on current user stack */ 441 sub sp, sp, #S_FRAME_SIZE 442 /* Save user registers (now in svc mode) r0-r12 */ 443 stmia sp, {r0 - r12} 444 445 ldr r2, IRQ_STACK_START_IN 446 /* get values for "aborted" pc and cpsr (into parm regs) */ 447 ldmia r2, {r2 - r3} 448 /* grab pointer to old stack */ 449 add r0, sp, #S_FRAME_SIZE 450 451 add r5, sp, #S_SP 452 mov r1, lr 453 /* save sp_SVC, lr_SVC, pc, cpsr */ 454 stmia r5, {r0 - r3} 455 /* save current stack into r0 (param register) */ 456 mov r0, sp 457 .endm 458 459 .macro get_bad_stack 460 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 461 462 /* save caller lr in position 0 of saved stack */ 463 str lr, [r13] 464 /* get the spsr */ 465 mrs lr, spsr 466 /* save spsr in position 1 of saved stack */ 467 str lr, [r13, #4] 468 469 /* prepare SVC-Mode */ 470 mov r13, #MODE_SVC 471 @ msr spsr_c, r13 472 /* switch modes, make sure moves will execute */ 473 msr spsr, r13 474 /* capture return pc */ 475 mov lr, pc 476 /* jump to next instruction & switch modes. */ 477 movs pc, lr 478 .endm 479 480 .macro get_bad_stack_swi 481 /* space on current stack for scratch reg. */ 482 sub r13, r13, #4 483 /* save R0's value. */ 484 str r0, [r13] 485 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 486 /* save caller lr in position 0 of saved stack */ 487 str lr, [r0] 488 /* get the spsr */ 489 mrs r0, spsr 490 /* save spsr in position 1 of saved stack */ 491 str lr, [r0, #4] 492 /* restore r0 */ 493 ldr r0, [r13] 494 /* pop stack entry */ 495 add r13, r13, #4 496 .endm 497 498/* 499 * exception handlers 500 */ 501 .align 5 502undefined_instruction: 503 get_bad_stack 504 bad_save_user_regs 505 bl do_undefined_instruction 506 507 .align 5 508software_interrupt: 509 get_bad_stack_swi 510 bad_save_user_regs 511 bl do_software_interrupt 512 513 .align 5 514prefetch_abort: 515 get_bad_stack 516 bad_save_user_regs 517 bl do_prefetch_abort 518 519 .align 5 520data_abort: 521 get_bad_stack 522 bad_save_user_regs 523 bl do_data_abort 524 525 .align 5 526not_used: 527 get_bad_stack 528 bad_save_user_regs 529 bl do_not_used 530 531 .align 5 532irq: 533 get_bad_stack 534 bad_save_user_regs 535 bl do_irq 536 537 .align 5 538fiq: 539 get_bad_stack 540 bad_save_user_regs 541 bl do_fiq 542#endif /* CONFIG_NAND_SPL */ 543